公开(公告)号：US20140177354A1

公开(公告)日：2014-06-26

申请号：US13725784

申请日：2012-12-21

Applicant: APPLE INC.

Inventor： Hitesh K. Gupta ,  Greg M. Hess ,  Naveen Javarappa

IPC: G11C7/00 ,  H03K19/00

CPC classification number: G11C7/00 ,  G11C29/1201 ,  G11C29/32 ,  G11C29/48 ,  H03K3/356121 ,  H03K3/356173 ,  H03K19/00

Abstract: A zero keeper circuit includes a dynamic input PFET connected to a source, an output, and a dynamic input. The circuit also includes a clock input NFET connected to the output, a pull-down node, and a clock input. The circuit also includes a dynamic input NFET connected to the pull-down node, a reference voltage, and the dynamic input. The circuit also includes a feedback PFET and a clock input PFET connected in series between the source and the output. The feedback PFET receives a feedback signal and the clock input PFET receives the clock input. The circuit also includes a feedback NFET connected to the output and the node. The feedback NFET is configured to couple the output to the node based on the feedback signal. The circuit also includes a NOR gate configured to provide the feedback signal based on the output and a bypass input.

Abstract translation: 零保持器电路包括连接到源，输出和动态输入的动态输入PFET。 电路还包括连接到输出的时钟输入NFET，下拉节点和时钟输入。 电路还包括连接到下拉节点的动态输入NFET，参考电压和动态输入。 电路还包括反馈PFET和在源极和输出端之间串联连接的时钟输入PFET。 反馈PFET接收反馈信号，时钟输入PFET接收时钟输入。 电路还包括连接到输出端和节点的反馈NFET。 反馈NFET被配置为基于反馈信号将输出耦合到节点。 电路还包括被配置为基于输出和旁路输入提供反馈信号的或非门。