公开(公告)号：US09696772B2

公开(公告)日：2017-07-04

申请号：US14186519

申请日：2014-02-21

Applicant: ARM LIMITED

Inventor： Nicolaas Klarinus Johannes Van Winkelhoff ,  Ali Alaoui

IPC: G06F1/24 ,  G11C7/20 ,  G11C7/24

CPC classification number: G06F1/24 ,  G11C7/20 ,  G11C7/24

Abstract: A memory protection device for controlling access to a memory and a method of controlling access to a memory are disclosed. A memory status value held by latch circuitry in the memory protection device determines whether the memory is an enabled or a disabled state. After power-up, a power-on-reset signal causes the memory status value to indicate the enabled state. In response to the assertion from a received control signal a memory kill signal is generated by the memory protection device which causes the memory status value to switch to its disabled state and the memory status value then cannot be changed back to the enabled state without a power reset. The memory status value being in the disabled state causes enable signal generation circuitry of the memory to openly be able to generate its read enable signal and write enable signal in a disabled state, thus preventing access to the memory.

公开(公告)号：US09036427B2

公开(公告)日：2015-05-19

申请号：US13943029

申请日：2013-07-16

Applicant: ARM LIMITED

Inventor： Nicolaas Klarinus Johannes Van Winkelhoff ,  Ali Alaoui ,  Pierre Lemarchand ,  Bastien Jean Claude Aghetti

IPC: G11C16/04 ,  G11C7/24 ,  G11C8/20 ,  G11C16/22 ,  G11C7/22

CPC classification number: G11C7/24 ,  G11C7/22 ,  G11C8/20 ,  G11C16/22

Abstract: The present invention provides an apparatus and method for erasing data in a memory device comprising an array of memory cells, and configured to operate from a clock signal. The apparatus includes erase circuitry, responsive to receipt of an erase signal in an asserted state, to perform a forced write operation independently of the clock signal in respect of each memory cell within a predetermined erase region of said array. Further, erase signal generation circuitry is configured to receive a control signal and to maintain said erase signal in a deasserted state provided that the control signal takes the form of a pulse signal having at least a predetermined minimum frequency between pulses. The erase signal generation circuitry is further configured to issue said erase signal in said asserted state if the control signal does not take the form of said pulse signal. Such an approach enables the security of a memory device to be improved, and in particular prevents hackers from taking advantage of data remanence effects, by ensuring that stored data is overwritten in an efficient, and clock independent, manner, triggered by assertion of an erase signal generated if a pulse-based control signal does not take it is expected form.

Abstract translation: 本发明提供了一种用于擦除存储器件中的数据的装置和方法，该存储器件包括存储器单元阵列，并被配置为从时钟信号进行操作。 该装置包括擦除电路，响应于在断言状态下的擦除信号的接收，以独立于与所述阵列的预定擦除区域内的每个存储器单元的时钟信号执行强制写入操作。 此外，擦除信号产生电路被配置为接收控制信号并且将所述擦除信号保持在无效状态，只要控制信号采取在脉冲之间具有至少预定的最小频率的脉冲信号的形式即可。 擦除信号产生电路还被配置为如果控制信号不采取所述脉冲信号的形式，则在所述断言状态下发出所述擦除信号。 这样一种方法可以改善存储器件的安全性，并且特别是通过确保存储的数据以有效和时钟独立的方式被覆盖而被防止黑客利用数据剩余效应 如果基于脉冲的控制信号不采用，则产生信号。