公开(公告)号：US20170364461A1

公开(公告)日：2017-12-21

申请号：US15612072

申请日：2017-06-02

Applicant: ARM LIMITED

Inventor： Daren CROXFORD ,  Sharjeel SAEED ,  Quinn CARTER ,  Michael Andrew CAMPBELL

IPC: G06F13/16

Abstract: A master device has a buffer for storing data transferred from, or to be transferred to, a memory system. Control circuitry issues from time to time a group of one or more transactions to request transfer of a block of data between the memory system and the buffer. Hardware or software mechanism can be provided to detect at least one memory load parameter indicating how heavily loaded the memory system is, and a group size of the block of data transferred per group can be varied based on the memory load parameter. By adapting the size of the block of data transferred per group based on memory system load, a better balance between energy efficiency and quality of service can be achieved.

公开(公告)号：US20180004678A1

公开(公告)日：2018-01-04

申请号：US15614644

申请日：2017-06-06

Applicant: ARM LIMITED

Inventor： Michal Karol BOGUSZ ,  Quinn CARTER ,  Andrew Brookfield SWAINE

IPC: G06F12/1027 ,  G06F12/02 ,  G06F12/1009

CPC classification number: G06F12/1027 ,  G06F12/0215 ,  G06F12/1009 ,  G06F2212/65 ,  G06F2212/654 ,  G06F2212/68

Abstract: An apparatus, system, and method for address translation are provided. Physical address information corresponding to virtual addresses is prefetched and stored, where at least some sequences of the virtual addresses are in a predefined order. The physical address information is prefetched based on identification information provided by a data processing activity, comprising at least a segment identifier and a portion of a virtual address to be translated. The storage has segments of entries, wherein each segment stores physical address information which corresponds to virtual addresses in a predefined order. This predefined order means that it is not necessary to store virtual addresses in the storage. Storage capacity and response speed are therefore gained.