公开(公告)号：US20220027191A1

公开(公告)日：2022-01-27

申请号：US16934355

申请日：2020-07-21

Applicant: Arm Limited

Inventor： Timothy Nicholas HAY ,  Nathan William WHITAKER ,  Haralds CAPKEVICS

IPC: G06F9/48 ,  G06F9/455

Abstract: An apparatus comprises an interrupt distributor to distribute virtual interrupts to one or more physical processors, each virtual interrupt to be handled by one of a plurality of virtual processors mappable to said one or more physical processors; and control circuitry to maintain virtual processor interrupt tracking information corresponding to a given virtual processor. The virtual processor interrupt tracking information includes a pending interrupt record tracking which types of virtual interrupts are pending for the given virtual processor, and separate from the pending interrupt record, a pending interrupt status indication indicating a pending interrupt status for the given virtual processor. The pending interrupt status indicates whether the number of pending virtual interrupts for the given virtual processor is zero.

公开(公告)号：US20220027190A1

公开(公告)日：2022-01-27

申请号：US16934353

申请日：2020-07-21

Applicant: Arm Limited

Inventor： Timothy Nicholas HAY ,  Haralds CAPKEVICS

IPC: G06F9/48 ,  G06F9/455 ,  G06F9/50 ,  G06F13/24

Abstract: Virtual processors are mappable to a number of physical processors. An interrupt distributor is responsible for distributing interrupt requests to a subset of the physical processors. An interface communicates with further interrupt distributors responsible for other physical processors. In response to an interrupt request to be handled by a target virtual processor, the interrupt distributor determines, based on cached virtual processor mapping information, whether to route the interrupt request to one of the subset of physical processors or to one of the further interrupt distributors. When a rejection response is received in response to an interrupt request routed to one of the further interrupt distributors, an update of the cached virtual processing mapping information is requested based on shared virtual processor mapping information, and a resent interrupt request is sent to a further interrupt distributor determined based on the shared virtual processor mapping information.

公开(公告)号：US20210271512A1

公开(公告)日：2021-09-02

申请号：US17056896

申请日：2019-05-01

Applicant: Arm Limited

Inventor： Timothy Nicholas HAY ,  Martin WEIDMANN ,  Michael Alexander KENNEDY ,  Andrew John TURNER

IPC: G06F9/48 ,  G06F9/52 ,  G06F9/54 ,  G06F9/455

Abstract: An interrupt controller comprises issue circuitry to issue interrupt requests to a processing element and control circuitry to detect presence of a race condition in association with at least one pending interrupt request to be issued, and to set a barrier indicator when the race condition has been resolved. In response to the race condition being present, the issue circuitry is configured to select one of the at least one pending interrupt requests, to issue to the processing element the selected pending interrupt request followed by a dummy request over a path that ensures that the processing element receives the selected pending interrupt request prior to receiving the dummy request. On receiving an acknowledgement indicating that the processing element has received the dummy request, the control circuitry is then configured to set the barrier indicator.

公开(公告)号：US20140143633A1

公开(公告)日：2014-05-22

申请号：US13681789

申请日：2012-11-20

Applicant: ARM LIMITED

Inventor： Michael Andrew CAMPBELL ,  Timothy Nicholas HAY

IPC: G06F11/10

CPC classification number: G06F11/10 ,  G06F11/1048

Abstract: An apparatus and method for correcting errors in data accessed from a memory device. A plurality of read symbols are read from a memory device. Syndrome information is then determined from the n data symbols and associated m error correction code symbols. Error correction circuitry uses the syndrome information in order to attempt to locate each read symbol containing an error and to correct the errors in each of those located read symbols. Error tracking circuitry tracks which memory regions the located read symbols containing an error originate from, and, on detecting an error threshold condition, sets at least one memory region as an erasure memory region. The correction circuitry treats each read symbol as a located read symbol containing an error, such that the read symbols to be located are not all randomly distributed and more than PMAX read symbols containing errors can be corrected.

Abstract translation: 一种用于校正从存储器件访问的数据中的错误的装置和方法。 从存储器件读取多个读取符号。 然后从n个数据符号和相关联的m个纠错码符号确定综合征信息。 错误校正电路使用校正子信息来尝试定位包含错误的每个读取符号，并纠正每个读取符号中的每个错误。 错误跟踪电路跟踪哪个存储器区域包含错误的位置的读取符号，并且在检测到错误阈值条件时，将至少一个存储器区域设置为擦除存储器区域。 校正电路将每个读取符号视为包含错误的位置读符号，使得要被定位的读符号不是全部随机分布，并且可以校正多于包含错误的PMAX读符号。