公开(公告)号：US20180293166A1

公开(公告)日：2018-10-11

申请号：US15479348

申请日：2017-04-05

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Klas Magnus BRUCE ,  Vasu KUDARAVALLI ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Joseph Michael PUSDESRIS

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0815 ,  G06F11/10

CPC classification number: G06F12/0811 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/62

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

公开(公告)号：US20160110202A1

公开(公告)日：2016-04-21

申请号：US14519697

申请日：2014-10-21

Applicant: ARM LIMITED

Inventor： Michael Alan FILIPPO ,  Matthew Paul ELWOOD ,  Umar FAROOQ ,  Adam GEORGE

IPC: G06F9/38

CPC classification number: G06F9/3844 ,  G06F9/3806 ,  G06F9/3848

Abstract: A data processing apparatus 2 contains branch prediction circuitry 10 including a micro branch target buffer 28, a full branch target buffer 30 and a global history buffer 32. The branch target buffer entries 40 contain history data 42, 44 which indicates whether or not a number of the following blocks of program instructions, subsequent to and sequential to a block of program instruction identified by that branch target buffer entry containing a branch instruction, do themselves contain any branch instructions. If the history data 42, 44 indicates that the following blocks of program instructions do not contain branches, then the operation of the branch prediction circuitry 28, 30, 32 is suppressed for these following blocks of program instructions so as to save energy.

Abstract translation: 数据处理装置2包含分支预测电路10，分支预测电路10包括微分支目标缓冲器28，全分支目标缓冲器30和全局历史缓冲器32.分支目标缓冲器条目40包含历史数据42,44，其指示数字 在由包含分支指令的分支目标缓冲器条目标识的程序指令块之后并且与之相连的程序指令的以下程序块本身包含任何分支指令。 如果历史数据42,44指示以下程序指令块不包含分支，则对于这些以下程序指令块来说，分支预测电路28,30,32的操作被抑制以便节省能量。

公开(公告)号：US20180095752A1

公开(公告)日：2018-04-05

申请号：US15281226

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Vasu KUDARAVALLI ,  Matthew Paul ELWOOD ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Michael FILIPPO

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F12/0875 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30196 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3848 ,  G06F2212/452

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.