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公开(公告)号：US20200174947A1
公开(公告)日：2020-06-04
申请号：US16327501
申请日：2016-10-19
Applicant: ARM LIMITED
Inventor： Alex James WAUGH , Dimitrios KASERIDIS , Klas Magnus BRUCE , Michael FILIPPO , Joseph Michael PUSDESRIS , Jamshed JALAL
IPC: G06F12/121 , G06F12/0815
Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.
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公开(公告)号：US20230418609A1
公开(公告)日：2023-12-28
申请号：US17851266
申请日：2022-06-28
Applicant: Arm Limited
CPC classification number: G06F9/30058 , G06F9/3861
Abstract: There is provided a data processing apparatus comprising history storage circuitry that stores sets of behaviours of helper instructions for a control flow instruction. Pointer storage circuitry stores pointers, each associated with one of the sets. The behaviours in the one of the sets are indexed according to one of the pointers associated with that one of the sets. Increment circuitry increments at least some of the pointers in response to an increment event and prediction circuitry determines a predicted behaviour of the control flow instruction using one of the sets of behaviours.
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公开(公告)号：US20220237478A1
公开(公告)日：2022-07-28
申请号：US17155665
申请日：2021-01-22
Applicant: Arm Limited
Inventor： Devin LAFFORD , Alexander Cole SHULYAK , Joseph Michael PUSDESRIS , Jacob Martin DeGASPERIS
Abstract: An apparatus comprises processing circuitry to perform data processing in response to instructions; prediction state storage circuitry to store prediction state information; prediction state training circuitry to train the prediction state information in response to events detected during processing of instructions by the processing circuitry; and prediction circuitry to predict, based on the prediction state information, a given speculative action to be performed in response to a given prediction trigger event; in which: the prediction circuitry varies, based on one or more current system resource conditions of the apparatus, at least one action selection criterion used to select which speculative action is to be performed.
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公开(公告)号：US20220129186A1
公开(公告)日：2022-04-28
申请号：US17078304
申请日：2020-10-23
Applicant: Arm Limited
Inventor： Ho-Seop KIM , Joseph Michael PUSDESRIS , Miles Robert DOOLEY
IPC: G06F3/06
Abstract: A request node is provided, that includes request circuitry for issuing outgoing memory access requests to a remote node. Status receiving circuitry receives statuses regarding remote memory access requests at the remote node and control circuitry controls at least one of a rate or an aggression at which the outgoing memory access requests are issued to the remote node in dependence on at least some of the statuses. The control circuitry is inhibited from controlling the rate or the aggression until multiple statuses are received.
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公开(公告)号：US20200097411A1
公开(公告)日：2020-03-26
申请号：US16140625
申请日：2018-09-25
Applicant: Arm Limited
Inventor： Joseph Michael PUSDESRIS , Miles Robert DOOLEY , Alexander Cole SHULYAK , Krishnendra NATHELLA , Dam SUNWOO
IPC: G06F12/0862 , G06F5/06 , G06F9/30
Abstract: Apparatuses and methods for prefetch generation are disclosed. Prefetching circuitry receives addresses specified by load instructions and can cause retrieval of a data value from an address before that address is received. Stride determination circuitry determines stride values as a difference between a current address and a previously received address. Plural stride values corresponding to a sequence of received addresses are determined. Multiple stride storage circuitry stores the plurality of stride values determined by the stride determination circuitry. New address comparison circuitry determines whether a current address corresponds to a matching stride value based on the plurality of stride values stored in the multiple stride storage circuitry. Prefetch initiation circuitry can causes a data value to be retrieved from a further address, wherein the further address is the current address modified by the matching stride value of the plurality of stride values. By the use of multiple stride values, more complex load address patterns can be prefetched.
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Patent Agency Ranking
公开(公告)号：US20230418766A1
公开(公告)日：2023-12-28
申请号：US18253621
申请日：2021-11-18
Applicant: Arm Limited
Inventor： Joseph Michael PUSDESRIS , Klas Magnus BRUCE , Jamshed JALAL , Dimitrios KASERIDIS , Gurunath RAMAGIRI , Ho-Seop KIM , Andrew John TURNER , Rania Hussein Hassan MAMEESH
IPC: G06F12/126 , G06F12/0811
CPC classification number: G06F12/126 , G06F12/0811
Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.
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公开(公告)号：US20230110541A1
公开(公告)日：2023-04-13
申请号：US17500309
申请日：2021-10-13
Applicant: Arm Limited
IPC: G06F12/0862 , G06F12/0811 , G06F12/1027 , G06F12/02
Abstract: A technique is provided for prefetching data items. An apparatus has a storage structure with a plurality of entries to store data items. The storage structure is responsive to access requests from processing circuitry to provide access to the data items. The apparatus has prefetch circuitry to prefetch data and correlation information storage to store correlation information for a plurality of data items. The correlation information identifies, for each of the plurality of data items, one or more correlated data items. The prefetch circuitry is configured to monitor the access requests from the processing circuitry. In response to detecting a hit in the correlation information storage for a particular access request that identifies a requested data item for which the correlation information storage stores correlation information, the prefetch circuitry is configured to prefetch the one or more correlated data items identified by the correlation information for the requested data item.
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公开(公告)号：US20220156078A1
公开(公告)日：2022-05-19
申请号：US16952661
申请日：2020-11-19
Applicant: Arm Limited
Abstract: In register renaming circuitry architectural registers specified in instructions are mapped to physical registers using a mapping table. Operations to be performed with respect to the physical registers are generated in dependence on the instructions and on the mapping table entries. When the mapping table has a mapping of a first instruction destination physical register for a first instruction destination architectural register specified in a first instruction, a second instruction specifying the first instruction destination architectural register as a second instruction source architectural register causes an adapted second operation to be generated corresponding to the second instruction using at least one first instruction source physical register as at least one second instruction source physical register. The adapted second operation incorporates a first operation corresponding to the first instruction.
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公开(公告)号：US20220107894A1
公开(公告)日：2022-04-07
申请号：US17064019
申请日：2020-10-06
Applicant: Arm Limited
Inventor： Joseph Michael PUSDESRIS
IPC: G06F12/0808 , G06F12/02 , G06F12/0811
Abstract: A technique is provided for controlling eviction from a storage structure. An apparatus has a storage structure with a plurality of entries to store data. The apparatus also has eviction control circuitry configured to maintain eviction control information in accordance with an eviction policy, the eviction policy specifying how the eviction control information is to be updated in response to accesses to the entries of the storage structure. The eviction control circuitry is responsive to a victim selection event to employ the eviction policy to select, with reference to the eviction control information, one of the entries to be a victim entry whose data is to be discarded from the storage structure. The eviction control circuitry is further configured to maintain, for each of one or more groups of entries in the storage structure, an indication of a most-recent entry. The most-recent entry is an entry in that group that was most recently subjected to at least a given type of access. For each group, in response to an access to a given entry of that group other than the most-recent entry for that group, the eviction control circuitry is configured to update the eviction control information according to the eviction policy. However, in response to an access to the most-recent entry for that group, the eviction control circuitry is configured to prevent an update to at least the eviction control information associated with the most-recent entry.
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公开(公告)号：US20210056034A1
公开(公告)日：2021-02-25
申请号：US16549291
申请日：2019-08-23
Applicant: Arm Limited
Inventor： Joseph Michael PUSDESRIS , Yasuo ISHII
IPC: G06F12/0891 , G06F9/30 , G06F12/0875
Abstract: A data processing apparatus is provided. It includes cache circuitry to store a plurality of items, each having an associated indicator. Processing circuitry executes instructions using at least some of the plurality of items. Fill circuitry inserts a new item into the cache circuitry. Eviction circuitry determines which of the plurality of items is to be a victim item based on the indicator, and evicts the victim item from the cache circuitry. Detection circuitry detects a state of the processing circuitry at a time that the new item is inserted into the cache circuitry, and sets the indicator in dependence on the state.
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