公开(公告)号：US20210064377A1

公开(公告)日：2021-03-04

申请号：US16550612

申请日：2019-08-26

Applicant: Arm Limited

Inventor： . ABHISHEK RAJA ,  Rakesh Shaji LAL ,  Michael FILIPPO ,  Glen Andrew HARRIS ,  Vasu KUDARAVALLI ,  Huzefa Moiz SANJELIWALA ,  Jason SETTER

IPC: G06F9/38 ,  G06F9/30 ,  G06F9/34

Abstract: A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, flushed instructions that appear after the status updating instruction in the instruction stream.

公开(公告)号：US20180293166A1

公开(公告)日：2018-10-11

申请号：US15479348

申请日：2017-04-05

Applicant: ARM Limited

Inventor： Michael FILIPPO ,  Klas Magnus BRUCE ,  Vasu KUDARAVALLI ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Joseph Michael PUSDESRIS

IPC: G06F12/0811 ,  G06F12/0875 ,  G06F12/0891 ,  G06F12/0815 ,  G06F11/10

CPC classification number: G06F12/0811 ,  G06F11/1064 ,  G06F12/0815 ,  G06F12/0875 ,  G06F12/0891 ,  G06F2212/452 ,  G06F2212/62

Abstract: A cache hierarchy and a method of operating the cache hierarchy are disclosed. The cache hierarchy comprises a first cache level comprising an instruction cache, and predecoding circuitry to perform a predecoding operation on instructions having a first encoding format retrieved from memory to generate predecoded instructions having a second encoding format for storage in the instruction cache. The cache hierarchy further comprises a second cache level comprising a cache and the first cache level instruction cache comprises cache control circuitry to control an eviction procedure for the instruction cache in which a predecoded instruction having the second encoding format which is evicted from the instruction cache is stored at the second cache level in the second encoding format. This enables the latency and power cost of the predecoding operation to be avoided when the predecoded instruction is then retrieved from the second cache level for storage in the first level instruction cache again.

公开(公告)号：US20180095752A1

公开(公告)日：2018-04-05

申请号：US15281226

申请日：2016-09-30

Applicant: ARM LIMITED

Inventor： Vasu KUDARAVALLI ,  Matthew Paul ELWOOD ,  Adam GEORGE ,  Muhammad Umar FAROOQ ,  Michael FILIPPO

IPC: G06F9/30 ,  G06F9/38 ,  G06F12/0875

CPC classification number: G06F12/0875 ,  G06F8/41 ,  G06F9/30145 ,  G06F9/3016 ,  G06F9/3017 ,  G06F9/30196 ,  G06F9/3808 ,  G06F9/382 ,  G06F9/3842 ,  G06F9/3844 ,  G06F9/3846 ,  G06F9/3848 ,  G06F2212/452

Abstract: An apparatus comprises processing circuitry, an instruction cache, decoding circuitry to decode program instructions fetched from the cache to generate macro-operations to be processed by the processing circuitry, and predecoding circuitry to perform a predecoding operation on a block of program instructions fetched from a data store to generate predecode information to be stored to the cache with the block of instructions. In one example the predecoding operation comprises generating information on how many macro-operations are to generated by the decoding circuitry for a group of one or more program instructions. In another example the predecoding operation comprises generating information indicating whether at least one of a given subset of program instructions within the prefetched block is a branch instruction.