公开(公告)号：US09753735B2

公开(公告)日：2017-09-05

申请号：US14596948

申请日：2015-01-14

Applicant: ARM Limited

Inventor： Andreas Due Engh-Halstvedt ,  Ian Victor Devereux ,  David Bermingham ,  Jakob Axel Fries ,  Oskar Lars Flordal

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/0855

CPC classification number: G06F9/3869 ,  G06F9/38 ,  G06F9/3816 ,  G06F9/3855 ,  G06F9/3867 ,  G06F12/0855 ,  G06F2212/455

Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbors within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.