公开(公告)号：US20240371070A1

公开(公告)日：2024-11-07

申请号：US18602592

申请日：2024-03-12

Applicant: Arm Limited

Inventor： Jakob Axel Fries ,  William Robert Stoye ,  Richard Edward Bruce

IPC: G06T15/00 ,  G06T15/06

Abstract: A graphics processor that is operable to perform ray tracing is disclosed. When it is determined that a ray tracing circuit of the graphics processor may require additional storage space to store test record entries to trace a ray, additional storage space is allocated for the ray tracing circuit to use to store test record entries to trace the ray.

公开(公告)号：US11023152B2

公开(公告)日：2021-06-01

申请号：US16510200

申请日：2019-07-12

Applicant: Arm Limited

Inventor： Jorn Nystad ,  Edvard Fielding ,  Jakob Axel Fries

IPC: G06F3/06 ,  G06T1/60

Abstract: When storing an array of data in memory, the data array is divided into a plurality of blocks, and for respective groups of the blocks that the data array has been divided into, a set of data representing the group of blocks that includes: for each block of the group of blocks, a set of data for that block of the group of blocks; and a size indication for each of one or more of the blocks of the group of blocks, the size indication for a block of a group of blocks indicating the size in memory of the set of data for that block of the group included in the stored set of data representing the group of blocks, is stored. A set of header data is also stored separately for each group of blocks of the data array.

公开(公告)号：US20210126736A1

公开(公告)日：2021-04-29

申请号：US17078047

申请日：2020-10-22

Applicant: Arm Limited

Inventor： Sven Ola Johannes Hugosson ,  Jakob Axel Fries ,  Hakan Lars-Goran Persson ,  Muhammad Ali Shami

IPC: H04L1/00 ,  H04L12/741

Abstract: When encoding a block of data elements in an array of data elements, the data values for data elements in the block are represented and stored in a data packet as truncated data values using a subset of one or more most significant bits of the respective bit sequences for the data values of the data elements. A rounding mode is selected from a plurality of available rounding modes that can be applied when decoding the block of data elements and an indication of the selected rounding mode is provided along with the encoded data packet. The rounding mode is associated with one or more rounding bit sequence(s) that can then be applied to the truncated data values when decoding the data packet to obtain decoded data values for the data elements in the block.

公开(公告)号：US10726519B2

公开(公告)日：2020-07-28

申请号：US15714037

申请日：2017-09-25

Applicant: Arm Limited

Inventor： Edvard Fielding ,  Jakob Axel Fries

IPC: G06T1/60 ,  G06T1/20 ,  G06T15/00 ,  G06F12/0811 ,  G06T15/04

Abstract: A graphics processing system includes a cache system for transferring texture data stored in memory to a graphics processing unit for use by the graphics processing unit when generating a render output. The cache system includes a first cache operable to receive texture data from the memory system, and a second cache operable to receive texture data from the first cache and to provide texture data to the graphics processing unit for use when generating a render output, and a data processing unit intermediate the first cache and the second cache and operable to process data stored in the first cache and to store the processed data in the second cache.

公开(公告)号：US20170287101A1

公开(公告)日：2017-10-05

申请号：US15469503

申请日：2017-03-25

Applicant: ARM Limited

Inventor： Lars Oskar Flordal ,  Toni Viki Brkic ,  Jakob Axel Fries

IPC: G06T1/20 ,  G06T11/40 ,  G06T1/60

CPC classification number: G06F3/064 ,  G06F3/0604 ,  G06F3/0673 ,  G06T1/20 ,  G06T1/60 ,  G06T11/40 ,  G06T2210/08 ,  G09G5/393 ,  G09G2360/12 ,  G09G2360/122

Abstract: A tile-based graphics processing pipeline includes rendering circuitry for rendering graphics fragments to generate rendered fragment data. Each graphics fragment has associated with it a set of sampling positions to be rendered. The pipeline also includes a tile buffer configured to store rendered fragment data for sampling positions prior to the rendered fragment data being written out to memory, write out circuitry configured to write a compressed representation of the rendered fragment data for a tile in the tile buffer to memory, and processing circuitry. The processing circuitry identities, based on the writing of rendered fragment data to the tile buffer, any blocks comprising sampling positions within a tile having the same data value associated with each sampling position in the block, and to, when such a block of sampling positions is identified, trigger the write out circuitry to write a compressed representation of the block to the memory.

公开(公告)号：US09753735B2

公开(公告)日：2017-09-05

申请号：US14596948

申请日：2015-01-14

Applicant: ARM Limited

Inventor： Andreas Due Engh-Halstvedt ,  Ian Victor Devereux ,  David Bermingham ,  Jakob Axel Fries ,  Oskar Lars Flordal

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/0855

CPC classification number: G06F9/3869 ,  G06F9/38 ,  G06F9/3816 ,  G06F9/3855 ,  G06F9/3867 ,  G06F12/0855 ,  G06F2212/455

Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbors within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.

公开(公告)号：US11914518B1

公开(公告)日：2024-02-27

申请号：US17949607

申请日：2022-09-21

Applicant: Arm Limited

Inventor： Yoav Asher Levy ,  Elad Kadosh ,  Jakob Axel Fries ,  Lior-Levi Bandal

IPC: G06F12/0884

CPC classification number: G06F12/0884 ,  G06F2212/1021

Abstract: A cache is provided having a plurality of entries for storing data. In response to a given access request, lookup circuitry performs a lookup operation in the cache to determine whether one of the entries in the cache is allocated to store data associated with the memory address indicated by the given access request, with a hit indication or a miss indication being generated dependent on the outcome of that lookup operation. During a single lookup period, the lookup circuitry is configured to perform lookup operations in parallel for up to N access requests. In addition, allocation circuitry is provided that is able to determine, during the single lookup period, at least N candidate entries for allocation from amongst the plurality of entries, and to cause one of the candidate entries to be allocated for each of the up to N access requests for which the lookup circuitry generates a miss indication.

公开(公告)号：US11600026B2

公开(公告)日：2023-03-07

申请号：US16739631

申请日：2020-01-10

Applicant: Arm Limited

Inventor： Samuel Martin ,  Jakob Axel Fries ,  Ozgur Ozkurt

IPC: G06T9/40 ,  G09G5/36

Abstract: A data processing system comprises encoding circuitry operable to encode arrays of data elements, decoding circuitry operable to decode encoded versions of arrays of data elements, and consumer circuitry operable to use arrays of data elements. Data indicative of a resolution that is to be used by the consumer circuitry for at least one region of the array of data elements is provided to the encoding circuitry, and the encoding circuitry uses the data indicative of the resolution that is to be used by the consumer circuitry to control the generation of the representation for representing at least one block that the array of data elements is divided into.

公开(公告)号：US20220027281A1

公开(公告)日：2022-01-27

申请号：US17305991

申请日：2021-07-19

Applicant: Arm Limited

Inventor： Olof Henrik Uhrenholt ,  Håkan Lars-Göran Persson ,  Jakob Axel Fries

IPC: G06F12/0888 ,  G06T1/60 ,  G06T9/00 ,  G06T1/20

Abstract: A data processing system includes a memory system, a processor and a cache system. The cache system includes a cache and a data encoder associated with the cache. The data encoder encodes blocks of uncompressed data having a particular data size for storing in the memory system. The processor is configured, when an array of data has a data size equal to the particular data size or is able to be combined with one or more other arrays of data already written to the cache to provide a plurality of arrays of data having a data size that is equal to the particular data size, to output the array of data from the processor to the data encoder, bypassing the cache, for encoding as or as part of a block of data having the particular data size.

公开(公告)号：US10395394B2

公开(公告)日：2019-08-27

申请号：US15610016

申请日：2017-05-31

Applicant: ARM Limited

Inventor： Lars Oskar Flordal ,  Jakob Axel Fries ,  Toni Viki Brkic

IPC: G06K9/46 ,  G06T9/40 ,  H04N19/11 ,  H04N19/176 ,  H04N19/182 ,  H04N19/186 ,  H04N19/96 ,  G06T15/00 ,  G09G5/39 ,  G06T9/00 ,  H04N19/15

Abstract: A method of encoding a block of an array of data elements comprises selectively writing out an encoded version of the block either that is encoded using a first encoding scheme, which provides encoded blocks of non-fixed data size, or that is encoded using a second encoding scheme, which provides encoded blocks of fixed data size. The selection of which version of the encoded block to write out is based on the size of the encoded block when encoded using the first encoding scheme. This provides the potential for the encoded block that is written out to be compressed in a more superior manner using the first encoding scheme where possible, while also providing an encoded block that has a predictable maximum compressed size.