公开(公告)号：US10475147B2

公开(公告)日：2019-11-12

申请号：US15428645

申请日：2017-02-09

Applicant: Arm Limited

Inventor： Steven John Price ,  Hakan Lars-Goran Persson ,  Ian Victor Devereux ,  Jussi Tuomas Pennala

IPC: G06T1/20 ,  G06T1/60 ,  G06F9/50

Abstract: A graphics processing system comprises a pair of graphics processing units that are connected to each other via communications bridges that can allow communication between the connected graphics processing units. One of the graphics processing units is operable to act as a master graphics processing unit controlling graphics processing operations on the other graphics processing unit which is operable as a slave graphics processing unit to perform graphics processing operations under the control of the master graphics processing unit. Each graphics processing unit of the pair of graphics processing units is also capable of operating in a standalone mode, in which the graphics processing unit operates independently of the other graphics processing unit to perform a graphics processing task.

公开(公告)号：US09753735B2

公开(公告)日：2017-09-05

申请号：US14596948

申请日：2015-01-14

Applicant: ARM Limited

Inventor： Andreas Due Engh-Halstvedt ,  Ian Victor Devereux ,  David Bermingham ,  Jakob Axel Fries ,  Oskar Lars Flordal

IPC: G06F9/38 ,  G06F12/08 ,  G06F12/0855

CPC classification number: G06F9/3869 ,  G06F9/38 ,  G06F9/3816 ,  G06F9/3855 ,  G06F9/3867 ,  G06F12/0855 ,  G06F2212/455

Abstract: A data processing system includes a processing pipeline for the parallel execution of a plurality of threads. An issue controller issues threads to the processing pipeline. A stall manager controls the stalling and unstalling of threads when a cache miss occurs within a cache memory. The issue controller issues the threads to the processing pipeline in accordance with both a main sequence and a pilot sequence. The pilot sequence is followed such that threads within the pilot sequence are issued at least a given time ahead of their neighbors within a main sequence. The given time corresponds approximately to the latency associated with a cache miss. The threads may be arranged in groups corresponding to blocks of pixels for processing within a graphics processing unit.

公开(公告)号：US09146870B2

公开(公告)日：2015-09-29

申请号：US13949434

申请日：2013-07-24

Applicant: ARM LIMITED

Inventor： Hedley James Francis ,  Robert Martin Elliott ,  Ian Victor Devereux ,  Daren Croxford

IPC: G06F13/38 ,  G06F12/08 ,  G06F12/12 ,  G06F9/52 ,  G06F3/03

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value. The processor is configured in response to the predefined request to perform the operation on data within the storage location allocated to the data item.

Abstract translation: 一种处理装置，包括：用于处理数据的几个处理器; 包括对所有处理器可访问的存储器以及对应于每个处理器的多个高速缓存的分级存储器系统，每个高速缓存可由对应的处理器访问，并且包括存储位置和对应的指示符。 还存在用于维持分层存储器系统中存储的数据的一致性的高速缓存一致性控制电路。 处理器被配置为响应于接收到对数据项执行操作的预定义请求，以确定与接收到请求的处理器相对应的高速缓存是否具有分配给数据项的存储位置。 如果不是，则处理装置被配置为：将缓存内的存储位置分配给数据项，设置与存储位置相对应的指示符，以指示存储位置正在存储增量值，将分配的存储位置中的数据设置为 一个初始值。 处理器被配置为响应于对分配给数据项的存储位置内的数据执行操作的预定义请求。

公开(公告)号：US09619929B2

公开(公告)日：2017-04-11

申请号：US14519620

申请日：2014-10-21

Applicant: ARM Limited

Inventor： Ian Victor Devereux ,  Simon Jones ,  Frode Heggelund ,  Toni Viki Brkic

IPC: G06T15/40 ,  G06T15/50 ,  G06T1/60 ,  G06T15/00 ,  G06T11/40

CPC classification number: G06T15/40 ,  G06T1/60 ,  G06T11/40 ,  G06T15/005 ,  G06T15/503

Abstract: A graphics processing apparatus and method of graphics processing is disclosed. Obscuration identification circuitry is configured to receive graphics fragments from rasterization circuitry and to identify an obscuration condition if a received graphics fragment, in combination with at least one previously received graphics fragment, will obscure at least one further previously received graphics fragment. Process killing circuitry is configured to prevent further processing occurring in the graphics processing apparatus with respect to the at least one further previously received graphics fragment if the obscuration identification circuitry identifies the obscuration condition.

公开(公告)号：US20150032970A1

公开(公告)日：2015-01-29

申请号：US13949434

申请日：2013-07-24

Applicant: Arm Limited

Inventor： Hedley James Francis ,  Robert Martin Elliott ,  Ian Victor Devereux ,  Daren Croxford

IPC: G06F12/08

CPC classification number: G06F12/0815 ,  G06F12/0811 ,  G06F12/12 ,  G06F2212/1016 ,  G06F2212/1028 ,  Y02D10/13

Abstract: A processing apparatus comprising: several processors for processing data; a hierarchical memory system comprising a memory accessible to all the processors, and several caches corresponding to each of the processors, each of the caches being accessible to the corresponding processor and comprising storage locations and corresponding indicators. There is also cache coherency control circuitry for maintaining coherency of data stored in the hierarchical memory system. The processors are configured to respond to receipt of a predefined request to perform an operation on a data item to determine if the cache corresponding to the processor receiving the request has a storage location allocated to the data item. If not, the processing apparatus is configured to: allocate a storage location within the cache to the data item, set the indicator corresponding to the storage location to indicate that the storage location is storing a delta value, set data in the allocated storage location to an initial value. The processor is configured in response to the predefined request to perform the operation on data within the storage location allocated to the data item.

Abstract translation: 一种处理装置，包括：用于处理数据的几个处理器; 包括对所有处理器可访问的存储器以及对应于每个处理器的多个高速缓存的分级存储器系统，每个高速缓存可由对应的处理器访问，并且包括存储位置和对应的指示符。 还存在用于维持分层存储器系统中存储的数据的一致性的高速缓存一致性控制电路。 处理器被配置为响应于接收到对数据项执行操作的预定义请求，以确定与接收到请求的处理器相对应的高速缓存是否具有分配给数据项的存储位置。 如果不是，则处理装置被配置为：将缓存内的存储位置分配给数据项，设置与存储位置相对应的指示符，以指示存储位置正在存储增量值，将分配的存储位置中的数据设置为 一个初始值。 处理器被配置为响应于对分配给数据项的存储位置内的数据执行操作的预定义请求。