公开(公告)号：US12175251B2

公开(公告)日：2024-12-24

申请号：US18107139

申请日：2023-02-08

Applicant: Arm Limited

Inventor： Glen Andrew Harris ,  Alexander Cole Shulyak ,  . Abhishek Raja ,  Bipin Prasad Heremagalur Ramaprasad ,  William Elton Burky ,  Li Ma ,  Michael David Achenbach ,  Nicholas Andrew Plante ,  Yasuo Ishii

IPC: G06F9/38

Abstract: There is provided an apparatus, method and medium. The apparatus comprises processing circuitry to process instructions and a reorder buffer identifying a plurality of entries having state information associated with execution of one or more of the instructions. The apparatus comprises allocation circuitry to allocate entries in the reorder buffer, and to allocate at least one compressed entry corresponding to a plurality of the instructions. The apparatus comprises memory access circuitry responsive to an address associated with a memory access instruction corresponding to access-sensitive memory and the memory access instruction corresponding to the compressed entry, to trigger a reallocation procedure comprising flushing the memory access instruction and triggering reallocation of the memory access instruction without the compression. The allocation circuitry is responsive to a frequency of occurrence of memory access instructions addressing the access-sensitive memory meeting a predetermined condition, to suppress the compression whilst the predetermined condition is met.

公开(公告)号：US12204785B2

公开(公告)日：2025-01-21

申请号：US17871332

申请日：2022-07-22

Applicant: Arm Limited

Inventor： Yasuo Ishii ,  Steven Daniel Maclean ,  Nicholas Andrew Plante ,  Muhammad Umar Farooq ,  Michael Brian Schinzler ,  Nicholas Todd Humphries ,  Glen Andrew Harris

IPC: G06F3/06

Abstract: There is provided a data processing apparatus in which decode circuitry receives a memory copy instruction containing an indication of a source area of memory, an indication of a destination area of memory, and an indication of a remaining copy length. In response to receiving the memory copy instruction, the decode circuitry generates at least one active memory copy operation or a null memory copy operation. The active memory copy operation causes one or more execution units to perform a memory copy from part of the source area of memory to part of the destination area of memory and the null memory copy operation leaves the destination area of memory unmodified.

公开(公告)号：US11663014B2

公开(公告)日：2023-05-30

申请号：US16550612

申请日：2019-08-26

Applicant: Arm Limited

Inventor： Abhishek Raja ,  Rakesh Shaji Lal ,  Michael Filippo ,  Glen Andrew Harris ,  Vasu Kudaravalli ,  Huzefa Moiz Sanjeliwala ,  Jason Setter

IPC: G06F9/38 ,  G06F9/312 ,  G06F9/30

CPC classification number: G06F9/3842 ,  G06F9/30043 ,  G06F9/30094 ,  G06F9/30101 ,  G06F9/3857 ,  G06F9/3861

Abstract: A data processing apparatus is provided that comprises fetch circuitry to fetch an instruction stream comprising a plurality of instructions, including a status updating instruction, from storage circuitry. Status storage circuitry stores a status value. Execution circuitry executes the instructions, wherein at least some of the instructions are executed in an order other than in the instruction stream. For the status updating instruction, the execution circuitry is adapted to update the status value based on execution of the status updating instruction. Flush circuitry flushes, when the status storage circuitry is updated, following instructions that appear after the status updating instruction in the instruction stream.

公开(公告)号：US11204773B2

公开(公告)日：2021-12-21

申请号：US16124247

申请日：2018-09-07

Applicant: Arm Limited

Inventor： William Elton Burky ,  Glen Andrew Harris ,  Yasuo Ishii

IPC: G06F9/38

Abstract: A data processing apparatus is provided. It includes processing circuitry for speculatively executing a plurality of instructions. Storage circuitry stores a current state of the processing circuitry and a plurality of previous states of the processing circuitry. Execution of the plurality of instructions changes the current state of the processing circuitry. Flush circuitry replaces, in response to a miss-prediction, the current state of the processing circuitry with a replacement one of the plurality of previous states of the processing circuitry.

公开(公告)号：US10310862B2

公开(公告)日：2019-06-04

申请号：US15464727

申请日：2017-03-21

Applicant: ARM Limited

Inventor： Robert Greg McDonald ,  Michael Filippo ,  Glen Andrew Harris

IPC: G06F9/302 ,  G06F9/312 ,  G06F9/52 ,  G06F9/38 ,  G06F9/30 ,  G06F9/32

Abstract: Data processing circuitry comprises out-of-order instruction execution circuitry to execute program instructions in an instruction execution order; a data store, to store information on a set of instructions for which execution has been initiated, the data store providing ordering information indicating the relative position of each instruction in the set of instructions with respect to a program code order; commit circuitry to commit the results of instructions executed by the instruction execution circuitry; one or more cumulative status registers configured to be set in response to a respective condition generated by execution of an instruction and then to remain set until an unset instruction is executed; and an identifier store, to store for at least those of the one or more cumulative status registers which are not currently set, an identifier of an instruction which is earliest in the program code order in the set of instructions and which generated a condition to set that cumulative status register.