公开(公告)号：US20140286096A1

公开(公告)日：2014-09-25

申请号：US13847743

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Yew Keong CHONG ,  Sanjay MANGAL ,  Hsin-Yu CHEN

IPC: G11C16/30

CPC classification number: G11C7/18 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level.

Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列组包括在读取操作之前将相关读取位线预充电到第一电压电平的电路。 每个存储单元具有连接在相关读取位线和不同于第一电压电平的第二电压电平之间的耦合电路。 在读取操作期间，与激活的存储器单元相关联的耦合电路根据存储在该激活的存储器单元内的数据值，选择性地将关联的读取位线朝向第二电压电平放电。 钳位电路将相关读取位线连接到第二电压电平。