公开(公告)号：US20150085586A1

公开(公告)日：2015-03-26

申请号：US14037413

申请日：2013-09-26

Applicant: ARM LIMITED

Inventor： Bo ZHENG ,  Jungtae KWON ,  Gus YEUNG ,  Yew Keong CHONG

IPC: G11C7/12 ,  G06F17/50

CPC classification number: G11C7/12 ,  G11C7/1096

Abstract: A memory device having an array of memory cells connected to a core voltage level, and access circuitry used to perform a write operation in order to write data into a plurality of addressed memory cells. At least one bit line associated with at least each column in the array containing an addressed memory cell is precharged to the peripheral voltage level prior to the write operation being performed. Word line driver circuitry is then configured to assert a word line signal at the core voltage level on the word line associated with the row of the array containing the addressed memory cells. Write multiplexing driver circuitry asserts a mux control signal to write multiplexing circuitry which then couples the bit line of each addressed memory cell to the write driver circuitry in dependence on the mux control signal identifying which column contains the addressed memory cells.

Abstract translation: 具有连接到核心电压电平的存储器单元阵列的存储器件，以及用于执行写入操作以便将数据写入到多个寻址的存储器单元中的存取电路。 在执行写入操作之前，至少与包含寻址的存储器单元的阵列中的每列相关联的位线被预充电到外围电压电平。 然后，字线驱动器电路被配置为在与包含寻址的存储器单元的阵列的行相关联的字线上的核心电压电平处断言字线信号。 写复用驱动器电路断言多路复用控制信号以写入多路复用电路，然后根据多路复用器控制信号将每个寻址的存储器单元的位线耦合到写入驱动器电路，该多路复用器控制信号识别哪个列包含寻址的存储器单元。

公开(公告)号：US20140286096A1

公开(公告)日：2014-09-25

申请号：US13847743

申请日：2013-03-20

Applicant: ARM Limited

Inventor： Yew Keong CHONG ,  Sanjay MANGAL ,  Hsin-Yu CHEN

IPC: G11C16/30

CPC classification number: G11C7/18 ,  G11C16/10 ,  G11C16/24 ,  G11C16/26

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, each row being coupled to an associated read word line, and each column forming at least one column group, where the memory cells of each column group are coupled to an associated read bit line. Each column group includes circuitry to precharge the associated read bit line to a first voltage level prior to the read operation. Each memory cell has coupling circuitry connected between the associated read bit line and a second voltage level different to the first voltage level. During read operation the coupling circuitry associated with the activated memory cell selectively discharges the associated read bit line towards the second voltage level dependent on the data value stored within that activated memory cell. The clamping circuitry connects the associated read bit line to the second voltage level.

Abstract translation: 存储器装置包括布置成多个行和列的存储器单元的阵列，每行耦合到相关联的读取字线，并且每列形成至少一个列组，其中每个列组的存储单元耦合到 相关的读位线。 每列组包括在读取操作之前将相关读取位线预充电到第一电压电平的电路。 每个存储单元具有连接在相关读取位线和不同于第一电压电平的第二电压电平之间的耦合电路。 在读取操作期间，与激活的存储器单元相关联的耦合电路根据存储在该激活的存储器单元内的数据值，选择性地将关联的读取位线朝向第二电压电平放电。 钳位电路将相关读取位线连接到第二电压电平。

公开(公告)号：US20210133027A1

公开(公告)日：2021-05-06

申请号：US16669906

申请日：2019-10-31

Applicant: Arm Limited

Inventor： Joel Thornton IRBY ,  Wendy Arnott ELSASSER ,  Mudit BHARGAVA ,  Yew Keong CHONG ,  George McNeil LATTIMORE ,  James Dennis DODRILL

IPC: G06F11/10 ,  G06N20/00 ,  G11C7/10 ,  G11C5/14

Abstract: A system-on-chip is provided that includes functional circuitry that performs a function. Control circuitry controls the function based one or more configuration parameters. Non-volatile storage circuitry includes a plurality of non-volatile storage cells each being adapted to write at least a bit of the one or more configuration parameters in a rewritable, persistent manner a plurality of times. Read circuitry locally accesses the non-volatile storage circuitry, obtains the one or more configuration parameters from the non-volatile storage circuitry and provides the one or more configuration parameters to the control circuitry. Write circuitry obtains the one or more configuration parameters and provides the one or more configuration parameters to the non-volatile storage circuitry by locally accessing the non-volatile storage circuitry.

公开(公告)号：US20150049563A1

公开(公告)日：2015-02-19

申请号：US13967879

申请日：2013-08-15

Applicant: ARM LIMITED

Inventor： Bikas MAITI ,  Yew Keong CHONG ,  Martin Jay KINKADE

IPC: G11C7/22

CPC classification number: G11C7/22 ,  G11C5/148 ,  G11C7/227 ,  G11C11/419

Abstract: A memory device includes an array of memory cells arranged as a plurality of rows and columns, a plurality of word lines, each word line being coupled to an associated row of memory cells, and a plurality of bit lines, each bit line being coupled to an associated column of memory cells. Access circuitry is coupled to the word lines and the bit lines in order to perform access operations in respect of selected memory cells within the array. Control circuitry controls operation of the access circuitry and includes self-timed path (STP) delay circuitry. The control circuitry employs the delay indication when controlling the access circuitry to perform said access operations. Voltage supply control circuitry switches the voltage supply to at least one portion of the STP delay circuitry between a peripheral voltage supply and an array voltage supply dependent on a control signal.

Abstract translation: 存储器件包括布置成多个行和列的存储器单元的阵列，多个字线，每个字线耦合到相关行的存储器单元，以及多个位线，每个位线耦合到 相关的存储单元列。 访问电路被耦合到字线和位线，以便对阵列内的所选存储单元执行访问操作。 控制电路控制接入电路的操作，并且包括自定时路径（STP）延迟电路。 控制电路在控制访问电路执行所述访问操作时采用延迟指示。 电压供应控制电路根据控制信号将外部电压源和阵列电压电源之间的电压供应切换到STP延迟电路的至少一部分。

公开(公告)号：US20160180896A1

公开(公告)日：2016-06-23

申请号：US14581229

申请日：2014-12-23

Applicant: ARM Limited

Inventor： Gus YEUNG ,  Fakhruddin Ali BOHRA ,  Mudit BHARGAVA ,  Andy Wangkun CHEN ,  Yew Keong CHONG

IPC: G11C7/10 ,  G11C7/22 ,  G11C7/12

CPC classification number: G11C7/1012 ,  G11C7/12 ,  G11C7/22

Abstract: A memory 2 includes a regular array of storage elements 4. A regular array of write multiplexers 8 is provided outside of the regular array of storage elements 4. The storage element pitch is matched to the write multiplexer pitch. The write multiplexers 10 support a plurality of write ports. When forming a memory design 2, a given instance of an array of write multiplexers 8 may be selected in dependence upon the desired number of write ports to support and this combined with a common form of storage element array 4.

Abstract translation: 存储器2包括存储元件4的规则阵列。写入多路复用器8的规则阵列被提供在存储元件4的规则阵列之外。存储元件间距与写多路复用器间距匹配。 写多路复用器10支持多个写端口。 当形成存储器设计2时，可以根据要支持的写入端口的期望数量来选择写入多路复用器8的阵列的给定实例，并且与常规形式的存储元件阵列4组合。

公开(公告)号：US20150009772A1

公开(公告)日：2015-01-08

申请号：US13936512

申请日：2013-07-08

Applicant: ARM Limited

Inventor： Wang-Kun CHEN ,  Yew Keong CHONG ,  Sriram THYAGARAJAN ,  Gus YEUNG

IPC: G11C5/14

CPC classification number: G11C11/417 ,  G11C5/148

Abstract: A memory has a normal mode and a power saving mode. The memory has bitline precharge circuitry which during the normal mode selectively couples a pair of bitlines to a precharge node to charge the bitlines to a given voltage level. During the power saving mode the bitlines are isolated from the precharge node. Voltage control circuitry is provided to maintain the precharge node at a first voltage level during the normal mode and at a second voltage level less than the first voltage level during the power saving mode. By reducing the voltage level at the precharge node during the power saving mode, the amount of inrush current occurring when switching from power saving mode to normal mode can be reduced, and this enables the wakeup time to be reduced when returning from power saving mode to normal mode.

Abstract translation: 存储器具有正常模式和省电模式。 存储器具有位线预充电电路，其在正常模式期间选择性地将一对位线耦合到预充电节点，以将位线充电到给定的电压电平。 在省电模式期间，位线与预充电节点隔离。 提供电压控制电路以在正常模式期间将预充电节点保持在第一电压电平，并且在省电模式期间处于小于第一电压电平的第二电压电平。 通过在省电模式下减小预充电节点处的电压电平，可以减少从省电模式切换到正常模式时所产生的浪涌电流量，并且能够在从省电模式返回时减少唤醒时间 正常模式。