公开(公告)号：US20210027148A1

公开(公告)日：2021-01-28

申请号：US16518444

申请日：2019-07-22

Applicant: Arm Limited

Inventor： Lingchuan MENG ,  John Wakefield BROTHERS, III ,  Jens OLSON ,  Jared Corey SMOLENS ,  Eric KUNZE ,  Ian Rudolf BRATT

IPC: G06N3/063 ,  H03M7/30

Abstract: A processor arranged to compress neural network activation data comprising an input module for obtaining neural network activation data. The processor also comprises a block creation module arranged to split the neural network activation data into a plurality of blocks; and a metadata generation module for generating metadata associated with at least one of the plurality of blocks. Based on the metadata generated a selection module selects a compression scheme for each of the plurality of blocks, and a compression module for applying the selected compression scheme to the corresponding block to produce compressed neural network activation data. An output module is also provided for outputting the compressed neural network activation data.

公开(公告)号：US20180157590A1

公开(公告)日：2018-06-07

申请号：US15825633

申请日：2017-11-29

Applicant: ARM Limited

Inventor： Håkan Lars-Göran PERSSON ,  Ian Rudolf BRATT ,  Andrew Brookfield SWAINE ,  Bruce James MATHEWSON

IPC: G06F12/0831 ,  G06F13/16

CPC classification number: G06F12/0833 ,  G06F13/1668 ,  G06F2212/621

Abstract: A filter unit comprises interface circuitry, to intercept coherency protocol transactions exchanged between a master device comprising a first cache and an interconnect for managing coherency between the first cache and at least one other cache or other master device. The filter unit has filtering circuitry for filtering the coherency protocol transactions in dependence on memory access permission data defining which regions of an address space the master device is allowed to access.

公开(公告)号：US20160188209A1

公开(公告)日：2016-06-30

申请号：US14969414

申请日：2015-12-15

Applicant: ARM Limited

Inventor： Andreas HANSSON ,  Ian Rudolf BRATT

IPC: G06F3/06 ,  G06F12/08

Abstract: An apparatus and method are provided for issuing access requests to a memory controller for a memory device whose memory structure consists of a plurality of sub-structures. The apparatus has a request interface for issuing access requests to the memory controller, each access request identifying a memory address. Within the apparatus static abstraction data is stored providing an indication of one or more of the sub-structures of the memory device, and the apparatus also stores an indication of outstanding access requests issued from the request interface. Next access request selection circuitry is then arranged to select from a plurality of candidate access requests a next access request to issue from the request interface. That selection is dependent on sub-structure indication data that is derived from application of an abstraction data function, using the static abstraction data, to the memory addresses of the candidate access requests and the outstanding access requests. Such an approach enables the apparatus to provide a series of access requests to the memory controller with the aim of enabling the memory controller to perform a more optimal access sequence with regard to the memory device.

Abstract translation: 提供了一种用于向存储器控制器发出访问请求的装置和方法，该存储器设备的存储器结构由多个子结构组成。 该装置具有用于向存储器控制器发出访问请求的请求接口，每个访问请求标识存储器地址。 在设备内，静态抽象数据被存储，提供存储设备的一个或多个子结构的指示，并且该设备还存储从请求接口发出的未完成的访问请求的指示。 然后，下一访问请求选择电路被布置成从多个候选访问请求中选择要从请求接口发出的下一访问请求。 该选择取决于从应用抽象数据功能（使用静态抽象数据）到候选访问请求的存储器地址和未完成的访问请求导出的子结构指示数据。 这样的方法使得设备能够向存储器控制器提供一系列访问请求，目的是使得存储器控制器能够针对存储器件执行更优化的访问顺序。