公开(公告)号：US20230289294A1

公开(公告)日：2023-09-14

申请号：US17999649

申请日：2021-05-20

Applicant: Arm Limited

Inventor： Andrew Brookfield SWAINE

IPC: G06F12/1009 ,  G06F12/1027

CPC classification number: G06F12/1009 ,  G06F12/1027

Abstract: Apparatus comprises address processing circuitry to detect information relating to an input memory address provided by address information tables; the address processing circuitry being configured to select an address information table at a given table level according to earlier information entry in an address information ;and the address table; and the address processing circuitry being configured to select an information entry in the selected address information table according to an offset component, the offset component being defined so that contiguous instances of that portion of the input memory address indicate contiguously addressed information entries; the address processing circuitry comprising detector circuitry to detect whether indicator data is set to indicate whether a group of one or more contiguously addressed information entries in the selected address information table provide at least one base address indicating a location within a contiguously addressed region comprising multiple address information tables at a later table level.

公开(公告)号：US20230176983A1

公开(公告)日：2023-06-08

申请号：US17906625

申请日：2021-01-26

Applicant: ARM LIMITED

Inventor： Jason PARKER ,  Andrew Brookfield SWAINE ,  Yuval ELAD ,  Martin WEIDMANN

IPC: G06F12/14 ,  G06F12/1045 ,  G06F12/0808

CPC classification number: G06F12/1425 ,  G06F12/1458 ,  G06F12/1063 ,  G06F12/0808

Abstract: Address translation circuitry (16) translates a virtual address specified by a memory access request issued by requester circuitry into a target physical address (PA). Requester-side filtering circuitry (20) performs a granule protection lookup based on the target PA and a selected physical address space (PAS) associated with the memory access request, to determine whether to allow the memory access request to be passed to a cache or interconnect. In the granule protection lookup, the requester-side filtering circuitry obtains granule protection information corresponding to a target granule of physical addresses including the target PA, which indicates at least one allowed PAS associated with the target granule, and blocks the memory access request when the granule protection information indicates that the selected PAS is not an allowed PAS.

公开(公告)号：US20180357178A1

公开(公告)日：2018-12-13

申请号：US15620017

申请日：2017-06-12

Applicant: ARM LIMITED

Inventor： Bruce James MATHEWSON ,  Phanindra Kumar MANNAVA ,  Matthew Lucien EVANS ,  Paul Gilbert MEYER ,  Andrew Brookfield SWAINE

IPC: G06F12/1036 ,  G06F12/0802 ,  G06F12/14 ,  G06F13/16

CPC classification number: G06F12/1036 ,  G06F12/0802 ,  G06F12/1425 ,  G06F13/1668

Abstract: Access control circuitry comprises: a detector to detect a memory address translation between a virtual memory address in a virtual memory address space and a physical memory address in a physical memory address space, provided in response to a translation request by further circuitry; an address translation memory, to store data representing a set of physical memory addresses previously provided to the further circuitry in response to translation requests by the further circuitry; an interface to receive a physical memory address from the further circuitry for a memory access by the further circuitry; a comparator to compare a physical memory address received from the further circuitry with the set of physical addresses stored by the address translation memory, and to permit access, by the further circuitry, to a physical address included in the set of one or more physical memory addresses.

公开(公告)号：US20200218665A1

公开(公告)日：2020-07-09

申请号：US16624430

申请日：2018-05-15

Applicant: ARM LIMITED

Inventor： Andrew Brookfield SWAINE

IPC: G06F12/1036 ,  G06F12/0891 ,  G06F12/0864 ,  G06F12/1009 ,  G06F12/0882

Abstract: An apparatus has an address translation cache (12, 16) having a number of cache entries (40) for storing address translation data which depends on one or more page table entries of page tables. Control circuitry (50) is responsive to an invalidation request specifying address information to perform an invalidation lookup operation to identify at least one target cache entry to be invalidated. The target cache entry is an entry for which the corresponding address translation data depends on at least one target page table entry corresponding to the address information. The control circuitry (50) selects one of a number of invalidation lookup modes to use for the invalidation lookup operation in dependence on page size information indicating the page size of the target page table entry. The different invalidation lookup modes correspond to different ways of identifying the target cache entry based on the address information.

公开(公告)号：US20200089634A1

公开(公告)日：2020-03-19

申请号：US16135149

申请日：2018-09-19

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Tushar P. RINGE ,  Anitha KONA ,  Andrew Brookfield SWAINE ,  Michael Andrew CAMPBELL

IPC: G06F13/28 ,  G06F13/16 ,  G06F13/364

Abstract: An apparatus and method are provided for processing burst read transactions. The apparatus has a master device and a slave device coupled to the master device via a connection medium. The master device comprises processing circuitry for initiating a burst read transaction that causes the master device to issue to the slave device, via the connection medium, an address transfer specifying a read address. The slave device is arranged to process the burst read transaction by causing a plurality of data items required by the burst read transaction to be obtained based on the read address specified by the address transfer, and by performing a plurality of data transfers over the connection medium in order to transfer the plurality of data items to the master device. The slave device has transfer identifier generation circuitry for generating, for each data transfer, a transfer identifier to be transmitted over the connection medium to identify which data item in the plurality of data items is being transferred by that data transfer. The master device has buffer circuitry to buffer data items received by the plurality of data transfers, and to employ the transfer identifier provided for each data transfer to cause the plurality of data items to be provided to the processing circuitry in a determined order irrespective of an order in which the data items are transferred to the master device via the plurality of data transfers. This can significantly reduce the overhead required to manage the supply of the data items to the processing circuitry in the required determined order.

公开(公告)号：US20170262381A1

公开(公告)日：2017-09-14

申请号：US15066380

申请日：2016-03-10

Applicant: ARM Limited

Inventor： Andrew Brookfield SWAINE

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F12/0864 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/68

Abstract: There is described a method and data processing apparatus configured to translate a virtual address into a physical address, the virtual address comprising an offset for a memory page, an index and a tag with the memory page having a variable size.

公开(公告)号：US20220327062A1

公开(公告)日：2022-10-13

申请号：US17753345

申请日：2020-08-26

Applicant: Arm Limited

Inventor： Andrew Brookfield SWAINE

IPC: G06F12/1027

Abstract: A type of translation lookaside buffer (TLB) invalidation instruction is described which specifically targets a first type of TLB which stores combined stage-1-and-2 entries which depend on both stage 1 translation data and the stage 2 translation data, and which is configured to ignore a TLB invalidation command which invalidates based on a first set of one or more invalidation conditions including an address-based invalidation condition depending on matching of intermediate address. A second type of TLB other than the first type ignores the invalidation command triggered by the first type of TLB invalidation instruction. This approach helps to limit the performance impact of stage 2 invalidations in systems supporting a combined stage-1-and-2 TLB which cannot invalidate by intermediate address.

公开(公告)号：US20220197791A1

公开(公告)日：2022-06-23

申请号：US17130474

申请日：2020-12-22

Applicant: Arm Limited

Inventor： Alexander Donald Charles CHADWICK ,  Andrew Brookfield SWAINE ,  Gareth James EVANS ,  Jonathan Curtis BEARD

IPC: G06F12/06 ,  G06F11/07

Abstract: An apparatus comprises memory access circuitry to access a memory system; a plurality of memory mapped registers, including at least an insert register and a producer pointer register; and control circuitry to perform an insert operation in response to receipt of an insert request from a requester device sharing access to the memory system. The insert request specifies an address mapped to the insert register and an indication of a payload. The insert operation includes controlling the memory access circuitry to write the payload to a location in the memory system selected based on a producer pointer value stored in the producer pointer register, and updating the producer pointer register to increment the producer pointer value.

公开(公告)号：US20220035740A1

公开(公告)日：2022-02-03

申请号：US16943121

申请日：2020-07-30

Applicant: Arm Limited

Inventor： Lorenzo DI GREGORIO ,  Andrew Brookfield SWAINE

IPC: G06F12/0811 ,  G06F12/0815 ,  G06F1/3296 ,  G06F1/3206

Abstract: An apparatus is described that has processing circuitry for performing operations, and a communication path employed by the processing circuitry to access a first memory. Switch circuitry, when activated, is connected to the communication path. The processing circuitry issues access commands specifying addresses to be accessed, where each address is mapped to location in a memory system in accordance with a system address map. The memory system comprises at least the first memory and a second memory. When in a particular mode, the processing circuitry performs operations that require access to only a subset of the locations provided in the first memory. The switch circuitry is arranged, whilst the processing circuitry is in the particular mode, to be activated in order to intercept the access commands issued over the communication path that specify addresses mapped by the system address map to locations within the subset of locations. Those intercepted access commands are redirected to locations within the second memory that are otherwise unused whilst the processing circuitry is in the particular mode. This can provide significant power consumption benefits.

公开(公告)号：US20160232106A1

公开(公告)日：2016-08-11

申请号：US15007529

申请日：2016-01-27

Applicant: ARM Limited

Inventor： Viswanath CHAKRALA ,  Andrew Brookfield SWAINE

IPC: G06F12/10

CPC classification number: G06F12/1027 ,  G06F2212/681

Abstract: Apparatus for data processing and a method of data processing are provided. Address translation storage stores address translations between first set addresses and second set addresses, and responds to a request comprising a first set address to return a response comprising a second set address if the required address translation is currently stored therein. If it is not the request is forwarded towards memory in a memory hierarchy. A pending request storage stores entries for received requests and in response to reception of the request, if a stored entry for a previous request indicates that the previous request has been forwarded towards the memory and an expected response to the previous request will provide the address translation, intercepts the request to delay its reception by the address translation storage. Bandwidth pressure on the address translation storage is thus relieved.

Abstract translation: 提供了数据处理装置和数据处理方法。 地址转换存储器存储在第一设置地址和第二设置地址之间的地址转换，并且如果当前存储所需的地址转换，则响应包括第一设置地址的请求以返回包括第二集合地址的响应。 如果不是将请求转发到内存层次结构中的内存。 待决请求存储器存储用于接收到的请求的条目并且响应于接收到请求，如果先前请求的存储条目指示先前的请求已经被转发到存储器，并且对先前请求的预期响应将提供地址转换 截取通过地址转换存储器延迟其接收的请求。 因此缓解了地址转换存储器上的带宽压力。