公开(公告)号：US09473114B1

公开(公告)日：2016-10-18

申请号：US14687526

申请日：2015-04-15

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  James Myers

IPC: H03L7/00 ,  H03K3/013 ,  H03K17/22 ,  H03K3/3565

CPC classification number: H03K17/223 ,  H03K3/3565

Abstract: Various implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.

Abstract translation: 本文描述的各种实现涉及用于上电复位检测的集成电路。 集成电路可以包括被配置为接收输入电压信号并且在输入电压信号的斜坡期间提供触发信号的第一级。 集成电路可以包括第二级，其被配置为从第一级接收触发信号，并且在通过至少一个晶体管的栅极泄漏的输入电压信号的斜坡期间提供输出电压信号。

公开(公告)号：US20160308514A1

公开(公告)日：2016-10-20

申请号：US14687526

申请日：2015-04-15

Applicant: ARM Limited

Inventor： Bal S. Sandhu ,  James Myers

IPC: H03K3/013 ,  H03K3/3565 ,  H03K17/22

CPC classification number: H03K17/223 ,  H03K3/3565

Abstract: Various implementations described herein are directed to an integrated circuit for power-on-reset detection. The integrated circuit may include a first stage configured to receive an input voltage signal and provide a triggering signal during ramp of the input voltage signal. The integrated circuit may include a second stage configured to receive the triggering signal from the first stage and provide an output voltage signal during ramp of the input voltage signal via gate leakage through at least one transistor.

Abstract translation: 本文描述的各种实现涉及用于上电复位检测的集成电路。 集成电路可以包括被配置为接收输入电压信号并且在输入电压信号的斜坡期间提供触发信号的第一级。 集成电路可以包括第二级，其被配置为从第一级接收触发信号，并且在通过至少一个晶体管的栅极泄漏的输入电压信号的斜坡期间提供输出电压信号。