公开(公告)号：US20230221866A1

公开(公告)日：2023-07-13

申请号：US18000761

申请日：2021-05-20

Applicant: Arm Limited

Inventor： Jamshed JALAL ,  Gurunath RAMAGIRI ,  Tushar P RINGE ,  Mark David WERKHEISER ,  Ashok Kumar TUMMALA ,  Dimitrios KASERIDIS

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673 ,  G06F3/0653

Abstract: A technique for handling memory access requests is described. An apparatus has an interconnect for coupling a plurality of requester elements with a plurality of slave elements. The requester elements are arranged to issue memory access requests for processing by the slave elements. An intermediate element within the interconnect acts as a point of serialisation to order the memory access requests issued by requester elements via the intermediate element. The intermediate element has tracking circuitry for tracking handling of the memory access requests accepted by the intermediate element. Further, request acceptance management circuitry is provided to identify a target slave element amongst the plurality of slave elements for that given memory access request, and to determine whether the given memory access request is to be accepted by the intermediate element dependent on an indication of bandwidth capability for the target slave element.

公开(公告)号：US20200174947A1

公开(公告)日：2020-06-04

申请号：US16327501

申请日：2016-10-19

Applicant: ARM LIMITED

Inventor： Alex James WAUGH ,  Dimitrios KASERIDIS ,  Klas Magnus BRUCE ,  Michael FILIPPO ,  Joseph Michael PUSDESRIS ,  Jamshed JALAL

IPC: G06F12/121 ,  G06F12/0815

Abstract: A data processing system (2) incorporates a first exclusive cache memory (8, 10) and a second exclusive cache memory (14). A snoop filter (18) located together with the second exclusive cache memory on one side of the communication interface (12) serves to track entries within the first exclusive cache memory. The snoop filter includes retention data storage circuitry to store retention data for controlling retention of cache entries within the second exclusive cache memory. Retention data transfer circuitry (20) serves to transfer the retention data to and from the retention data storage circuitry within the snoop filter and the second cache memory as the cache entries concerned are transferred between the second exclusive cache memory and the first exclusive cache memory.

公开(公告)号：US20170168876A1

公开(公告)日：2017-06-15

申请号：US15296283

申请日：2016-10-18

Applicant: ARM Limited

Inventor： Ashok Kumar TUMMALA ,  Jamshed JALAL ,  Paul Gilbert MEYER ,  Dimitrios KASERIDIS

IPC: G06F9/52 ,  G06F9/50

Abstract: A method, system, and device provide for the streaming of ordered requests from one or more Senders to one or more Receivers over an un-ordered interconnect while mitigating structural deadlock conditions.

公开(公告)号：US20230418766A1

公开(公告)日：2023-12-28

申请号：US18253621

申请日：2021-11-18

Applicant: Arm Limited

Inventor： Joseph Michael PUSDESRIS ,  Klas Magnus BRUCE ,  Jamshed JALAL ,  Dimitrios KASERIDIS ,  Gurunath RAMAGIRI ,  Ho-Seop KIM ,  Andrew John TURNER ,  Rania Hussein Hassan MAMEESH

IPC: G06F12/126 ,  G06F12/0811

CPC classification number: G06F12/126 ,  G06F12/0811

Abstract: Aspects of the present disclosure relate to an apparatus comprising processing circuitry, first cache circuitry and second cache circuitry, wherein the second cache circuitry has an access latency higher than an access latency of the first cache circuitry. The second cache circuitry is responsive to receiving a request for data stored within the second cache circuitry to identify said data as pseudo-invalid data and provide said data to the first cache circuitry. The second cache circuitry is responsive to receiving an eviction indication, indicating that the first cache circuitry is to evict said data, to, responsive to determining that said data has not been modified since said data was provided to the first cache circuitry, identify said pseudo-invalid data as valid data.