公开(公告)号：US20160321182A1

公开(公告)日：2016-11-03

申请号：US15099119

申请日：2016-04-14

Applicant: ARM Limited

Inventor： Roko GRUBISIC ,  Hakan PERSSON ,  Neil Andrew JAMESON

IPC: G06F12/08 ,  G06F12/12 ,  G06F12/10 ,  G06F9/46

CPC classification number: G06F12/0833 ,  G06F12/1027 ,  G06F2212/652 ,  G06F2212/681 ,  G06F2212/683

Abstract: An apparatus has a cache configured to store entries which correspond to blocks of addresses having one of a plurality of sizes as selected by a control device. When the control device has not yet indicated which size to use, cache access circuitry assumes a default size which is greater than at least one of the plurality of sizes.

Abstract translation: 一种装置具有缓存，其被配置为存储对应于由控制装置选择的具有多个尺寸中的一个的地址块的条目。 当控制设备尚未指示要使用哪个大小时，高速缓存访​​问电路采用大于多个尺寸中的至少一个的默认大小。