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    Improving the responsiveness of an apparatus to certain interrupts
    1.
    发明授权
    Improving the responsiveness of an apparatus to certain interrupts 有权

    公开(公告)号：US11275607B2

    公开(公告)日：2022-03-15

    申请号：US16821151

    申请日：2020-03-17

    Applicant: Arm Limited

    Inventor： Peter Richard Greenhalgh ,  Antony John Penton

    IPC: G06F13/24 ,  G06F9/48 ,  G06F9/38 ,  G06F9/54 ,  G06F9/46 ,  G06F9/32

    Abstract: An apparatus and method are described, the apparatus comprising processing circuitry to perform data processing operations, microarchitecture circuitry used by the processing circuitry during performance of the data processing operations, and an interface to receive interrupt requests. The processing circuitry is responsive to a received interrupt request to perform an interrupt service routine, and the apparatus comprises prediction circuitry to determine a predicted time of reception of a next interrupt of at least one given type. The apparatus also comprises microarchitecture control circuitry arranged to vary a configuration of the microarchitecture circuitry between a performance based configuration and a responsiveness based configuration in dependence on the predicted time, so as to seek to increase the responsiveness of the apparatus to interrupts as the predicted time is approached.

    Allowing deletion of a dispatched instruction from an instruction queue when sufficient processor resources are predicted for that instruction
    2.
    发明授权
    Allowing deletion of a dispatched instruction from an instruction queue when sufficient processor resources are predicted for that instruction 有权

    公开(公告)号：US10095518B2

    公开(公告)日：2018-10-09

    申请号：US14941840

    申请日：2015-11-16

    Applicant: ARM LIMITED

    Inventor： Andrew James Antony Lees ,  Ian Michael Caulfield ,  Peter Richard Greenhalgh

    IPC: G06F9/30

    Abstract: Instruction queue circuitry maintains an instruction queue to store fetched instructions. Instruction decode circuitry decodes instructions dispatched from the queue. The instruction decode circuitry allocates processor resource(s) for use in execution of the decoded instruction. Detection circuitry detect, for an instruction to be dispatched from a given instruction queue, a prediction indicating whether sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry. Dispatch circuitry dispatches an instruction from the queue to the instruction decode circuitry and allows deletion of the dispatched instruction from that instruction queue when the prediction indicates that sufficient processor resources are predicted to be available for allocation to that instruction by the instruction decode circuitry.

    Instruction prefetch throttling using instruction count and branch prediction
    3.
    发明授权
    Instruction prefetch throttling using instruction count and branch prediction 有权
    指令预取调节使用指令计数和分支预测

    公开(公告)号：US09477479B2

    公开(公告)日：2016-10-25

    申请号：US14301991

    申请日：2014-06-11

    Applicant: ARM LIMITED

    Inventor： Peter Richard Greenhalgh

    IPC: G06F9/38 ,  G06F9/32 ,  G06F9/30

    CPC classification number: G06F9/3806 ,  G06F9/3804 ,  G06F9/3869

    Abstract: A sequence of buffered instructions includes branch instructions. Branch prediction circuitry predicts if each branch instruction will result in a taken branch when executed. Normally, the fetch circuitry retrieves speculative instructions between the time that a source branch instruction is retrieved and the prediction if that source branch instruction will result in the taken branch. If the source branch instruction is predicted as taken, then the speculative instructions are discarded, and a count value indicates a number of instructions in the sequence between that source branch instruction and a subsequent branch instruction in the sequence that is also predicted as taken. Responsive to a subsequent occurrence of the source branch instruction predicted as taken, a throttled mode limits the number of instructions subsequently retrieved dependent on the count value, and then any further instructions are not retrieved for a number of clock cycles.

    Abstract translation: 缓冲指令序列包括分支指令。 分支预测电路预测每个分支指令是否会在执行时导致采集分支。 通常，提取电路在检索源分支指令的时间和如果该源分支指令将导致所采取的分支之间的预测时，检索推测指令。 如果源分支指令被预测为采取，则推测性指令被丢弃，并且计数值指示在该源分支指令与序列中的后续分支指令之间的序列中的指令数目，其也被预测为采用。 响应于随后发生的预测的源分支指令，节流模式限制随后检索的指令数量，取决于计数值，然后在多个时钟周期内不检索任何进一步的指令。

    Processor and method for processing instructions using at least one processing pipeline
    4.
    发明授权
    Processor and method for processing instructions using at least one processing pipeline 有权
    用于使用至少一个处理流水线处理指令的处理器和方法

    公开(公告)号：US09213547B2

    公开(公告)日：2015-12-15

    申请号：US13826553

    申请日：2013-03-14

    Applicant: ARM LIMITED

    Inventor： Ian Michael Caulfield ,  Peter Richard Greenhalgh ,  Max John Batley

    IPC: G06F9/30 ,  G06F9/00

    CPC classification number: G06F9/30079 ,  G06F9/3836 ,  G06F9/3875 ,  G06F9/3885

    Abstract: A processor has a processing pipeline with first, second and third stages. An instruction at the first stage takes fewer cycles to reach the second stage then the third stage. The second and third stages each have a duplicated processing resource. For a pending instruction which requires the duplicated resource and can be processed using the duplicated resource at either of the second and third stages, the first stage determines whether a required operand would be available when the pending instruction would reach the second stage. If the operand would be available, then the pending instruction is processed using the duplicated resource at the second stage, while if the operand would not be available in time then the instruction is processed using the duplicated resource in the third pipeline stage. This technique helps to reduce delays caused by data dependency hazards.

    Abstract translation: 处理器具有第一，第二和第三阶段的处理流水线。 第一阶段的指令需要更少的周期才能到达第二阶段，然后到第三阶段。 第二和第三阶段各有一个重复的处理资源。 对于要求复制的资源并且可以使用第二级和第三级中的任一级的重复资源来处理的等待指令，第一级确定当待命指令将到达第二级时所需的操作数是否可用。 如果操作数可用，则在第二阶段使用重复的资源处理挂起的指令，而如果操作数在时间上不可用，则使用第三流水线阶段中的重复资源处理指令。 这种技术有助于减少数据依赖性危害造成的延误。

    Apparatus and method for controlling allocation of data into a cache storage
    8.
    发明授权
    Apparatus and method for controlling allocation of data into a cache storage 有权

    公开(公告)号：US10394716B1

    公开(公告)日：2019-08-27

    申请号：US15946848

    申请日：2018-04-06

    Applicant: Arm Limited

    Inventor： Frederic Claude Marie Piry ,  Peter Richard Greenhalgh ,  Ian Michael Caulfield ,  Albin Pierrick Tonnerre ,  Jeffrey Allen Kehl

    IPC: G06F12/08 ,  G06F12/0871 ,  G06F12/0808 ,  G06F9/30 ,  G06F9/38 ,  G06F12/14

    Abstract: An apparatus and method are provided for controlling allocation of data into cache storage. The apparatus comprises processing circuitry for executing instructions, and a cache storage for storing data accessed when executing the instructions. Cache control circuitry is arranged, while a sensitive allocation condition is determined to exist, to be responsive to the processing circuitry speculatively executing a memory access instruction that identifies data to be allocated into the cache storage, to allocate the data into the cache storage and to set a conditional allocation flag in association with the data allocated into the cache storage. The cache control circuitry is then responsive to detecting an allocation resolution event, to determine based on the type of the allocation resolution event whether to clear the conditional allocation flag such that the data is thereafter treated as unconditionally allocated, or to cause invalidation of the data in the cache storage. Such an approach can reduce the vulnerability of a cache to speculation-based cache timing side-channel attacks.

    Mode switching in dependence upon a number of active threads
    10.
    发明授权
    Mode switching in dependence upon a number of active threads 有权

    公开(公告)号：US10705587B2

    公开(公告)日：2020-07-07

    申请号：US15133329

    申请日：2016-04-20

    Applicant: ARM LIMITED

    Inventor： Peter Richard Greenhalgh ,  Simon John Craske ,  Ian Michael Caulfield ,  Max John Batley ,  Allan John Skillman ,  Antony John Penton

    IPC: G06F9/38 ,  G06F1/3206 ,  G06F1/3287 ,  G06F9/30 ,  G06F1/3234 ,  G06F1/3237

    Abstract: Apparatus for processing data is provided with fetch circuitry for fetching program instructions for execution from one or more active threads of instructions having respective program counter values. Pipeline circuitry has a first operating mode and a second operating mode. Mode switching circuitry switches the pipeline circuitry, between the first operating mode and the second operating mode in dependence upon a number of active threads of program instructions having program instructions available to be executed. The first operating mode has a lower average energy consumption per instruction executed than the second operating mode and the second operating mode has a higher average rate of instruction execution for a single thread than the first operating mode. The first operating mode may utilise a barrel processing pipeline to perform interleaved multiple thread processing. The second operating mode may utilise an out-of-order processing pipeline for performing out-of-order processing.

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