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公开(公告)号：US20250068420A1
公开(公告)日：2025-02-27
申请号：US18734396
申请日：2024-06-05
Applicant: Arm Limited
Inventor： Daren Croxford , Sharjeel Saeed , Isidoros Sideris
Abstract: Data processing systems comprising a data processor, the data processor comprising an execution unit and storage for storing input data values for use by and/or output data values generated by the execution unit when executing instructions to perform data processing operations, and methods of control thereof, in which control of storage of data values for data source(s) of the storage is based on indication(s), in instruction(s) requiring use of data source(s) for a data processing operation, that one or more data values in the data source(s) are no longer required to be retained.
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公开(公告)号：US10514928B2
公开(公告)日：2019-12-24
申请号：US14663858
申请日：2015-03-20
Applicant: ARM LIMITED
Inventor： Isidoros Sideris , Daren Croxford , Andrew Burdass
IPC: G06F9/38 , G06F9/318 , G06F1/3287 , G06F9/30 , G06F1/3234 , G06F1/3203 , G06F1/329
Abstract: A data processing apparatus has control circuitry for detecting whether a first micro-operation to be processed by a first processing lane would give the same result as a second micro-operation processed by a second processing lane. If they would give the same result, then the first micro-operation is prevented from being processed by the first processing lane and the result of the second micro-operation is output as the result of the first micro-operation. This avoids duplication of processing, to save energy for example.
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公开(公告)号：US11900522B2
公开(公告)日：2024-02-13
申请号：US17821666
申请日：2022-08-23
Applicant: Arm Limited
Inventor： Isidoros Sideris , Péter Sonkoly , Adrian Pereiro Castro
CPC classification number: G06T15/005 , G06F9/3887
Abstract: Disclosed is a method of handling thread termination events within a graphics processor when a group of plural execution lanes are executing in a co-operative state. When a group of lanes is in the co-operative state, in response to the graphics processor encountering an event that means that a subset of one or more execution threads associated with the group of execution lanes in the co-operative state should be terminated: it is determined whether a condition to immediately terminate the subset of one or more execution threads is met. When the condition is not met, the group of execution lanes continue their execution in the co-operative state, but a record is stored to track that the threads in the subset of one or more execution threads should subsequently be terminated.
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公开(公告)号：US20240036932A1
公开(公告)日：2024-02-01
申请号：US18359002
申请日：2023-07-26
Applicant: Arm Limited
Inventor： Daren Croxford , Sharjeel Saeed , Isidoros Sideris
CPC classification number: G06F9/505 , G06T15/005
Abstract: Disclosed herein is a graphics processor that comprises a programmable execution unit operable to execute programs to perform graphics processing operations. The graphics processor further comprises a dedicated machine learning processing circuit operable to perform processing operations for machine learning processing tasks. The machine learning processing circuit is in communication with the programmable execution unit internally to the graphics processor. In this way, the graphics processor can be configured such that machine learning processing tasks can be performed by the programmable execution unit, the machine learning processing circuit, or a combination of both, with the different units being able to message each other accordingly to control the processing.
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公开(公告)号：US11276137B1
公开(公告)日：2022-03-15
申请号：US17201229
申请日：2021-03-15
Applicant: Arm Limited
Inventor： Isidoros Sideris , Stephane Forey , William Robert Stoye , John David Robson
Abstract: There is provided a graphics processor comprising a programmable execution unit operable to execute programs for respective execution thread groups. An eviction checking circuit is provided that is configured to check instructions as they are being fetched for execution from an instruction cache to determine whether the instruction includes any conditional eviction conditions that if not met indicate that the program to which the instruction relates should not continue to be executed for the group of execution threads. The eviction checking circuit is then configured to check whether any conditional eviction conditions are satisfied at this point and either allow the execution unit to continue program execution or cause the thread group to be evicted.
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Patent Agency Ranking
6.发明授权公开(公告)号：US12223325B2
公开(公告)日：2025-02-11
申请号：US18357503
申请日：2023-07-24
Applicant: Arm Limited
Inventor： Daren Croxford , Isidoros Sideris
Abstract: A data processor is disclosed in which groups of execution threads comprising a thread group can execute a set of instructions in lockstep, and in which a plurality of execution lanes can perform processing operations for the execution threads. In response to an execution thread issuing circuit determining whether a portion of active threads of a first thread group and a portion of active threads of a second thread group use different execution lanes of the plurality of execution lanes, the execution thread issuing circuit issuing both the portion of active threads of a first thread group and a portion of active threads of a second thread group for execution. This can have the effect of increasing data processor efficiency, thereby increasing throughput and reducing latency.
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公开(公告)号：US20240311949A1
公开(公告)日：2024-09-19
申请号：US18262963
申请日：2022-02-01
Applicant: Arm Limited
Inventor： Isidoros Sideris , Tord Kvestad Oygard , Per Kristian Kjoll , Ole Magnus Ruud
CPC classification number: G06T1/20 , G06F9/505 , G06T11/40 , G06T2210/52
Abstract: There is provided a graphics processor (10) comprising a primitive processing circuit operable to process graphics primitives into respective fragment work items to be rendered by a rendering circuit (22). The primitive processing circuit generates one or more queues (18A, 18B) of fragment work items for rendering that contain fragment work items corresponding to multiple, different sources of fragment work items. The graphics processor (10) is configured to issue fragment work items to the rendering circuit (22) in an interleaved fashion such that rendering of fragment work items from a first source of fragment work items can thereby be interleaved with rendering of fragment work items from a second source of fragment work items.
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公开(公告)号：US09817466B2
公开(公告)日：2017-11-14
申请号：US14663831
申请日：2015-03-20
Applicant: ARM LIMITED
Inventor： Isidoros Sideris , Daren Croxford , Andrew Burdass
CPC classification number: G06F1/3243 , G06F9/3808 , G06F9/3826 , G06F9/3832 , G06F9/3869 , Y02D10/152
Abstract: A data processing apparatus has control circuitry for detecting whether a current micro-operation to be processed by a processing pipeline would give the same result as an earlier micro-operation. If so, then the current micro-operation is passed through the processing pipeline, with at least one pipeline stage passed by the current micro-operation being placed in a power saving state during a processing cycle in which the current micro-operation is at that pipeline stage. The result of the earlier micro-operation is then output as a result of said current micro-operation. This allows power consumption to be reduced by not repeating the same computation.
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公开(公告)号：US20230385106A1
公开(公告)日：2023-11-30
申请号：US18323793
申请日：2023-05-25
Applicant: Arm Limited
Inventor： Isidoros Sideris , Daren Croxford , Edvard Sorgard
CPC classification number: G06F9/4881 , G06F9/3877
Abstract: A fault detection scheme for a data processor that comprises a programmable execution unit operable to execute programs to perform processing operations, and in which when executing a program, the execution unit executes the program for respective execution threads, each execution thread corresponding to a respective work item. In order to detect faults, a set of two or more identical execution threads is generated. The identical execution threads when executed perform identical processing for the same work item and a result of the processing of the same work item can thus be compared to determine whether there is a fault associated with the data processor.
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公开(公告)号：US10761885B2
公开(公告)日：2020-09-01
申请号：US16044747
申请日：2018-07-25
Applicant: ARM Limited
Inventor： Isidoros Sideris , Eugenia Cordero-Crespo , Amir Kleen
Abstract: An apparatus and method are provided for executing thread groups. The apparatus comprises scheduling circuitry for selecting for execution a first thread group from a plurality of thread groups, and thread processing circuitry that is responsive to the scheduling circuitry to execute active threads of the first thread group in dependence on a common program counter shared between the active threads. In response to an exit event occurring for the first thread group, the thread processing circuitry determines whether a program counter check condition is present, and this can be used to trigger program counter checking circuitry to perform a program counter check operation to update the common program counter and an active thread indication for the first thread group. The thread processing circuitry is provided with register storage in which program counter information for each thread of the first thread group can be stored, and the program counter checking circuitry is arranged to have access to that register storage when performing the program counter check operation. Further, the scheduling circuitry is arranged to select, for execution by the thread processing circuitry, a different thread group whilst awaiting performance of the program counter check operation by the program counter checking circuitry for the first thread group. This provides an area efficient mechanism for handling divergence and re-convergence of threads within thread groups, in a manner that avoids impacting performance.
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