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公开(公告)号：US20220327009A1
公开(公告)日：2022-10-13
申请号：US17225674
申请日：2021-04-08
Applicant: Arm Limited
Inventor： Jonathan Curtis BEARD , Curtis Glenn DUNHAM , Andreas Lars SANDBERG , Roxana RUSITORU
IPC: G06F9/54 , G06F15/78 , G06F12/1009 , G06F12/02
Abstract: Message passing circuitry comprises lookup circuitry responsive to a producer request indicating message data provided on a target message channel by a producer node of a system-on-chip, to obtain, from a channel consumer information structure, selected channel consumer information associated with a given consumer node subscribing to the target message channel. Control circuitry writes the message data to a location associated with an address in a consumer-defined region of address space determined based on the selected channel consumer information. When an event notification condition is satisfied for the target message channel and the given consumer node, and an event notification channel is to be used, event notification data is written to a location associated with an address in a consumer-defined region of address space determined based on event notification channel consumer information associated with the event notification channel.
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公开(公告)号：US20190018785A1
公开(公告)日：2019-01-17
申请号：US15819328
申请日：2017-11-21
Applicant: Arm Limited
Inventor： Jonathan Curtis BEARD , Roxana RUSITORU , Curtis Glenn DUNHAM
IPC: G06F12/1009 , G06F12/0802
CPC classification number: G06F12/1009 , G06F12/0653 , G06F12/0802 , G06F12/0862 , G06F12/1036 , G06F12/1063 , G06F12/1072 , G06F12/1081 , G06F12/109 , G06F2212/1044 , G06F2212/152 , G06F2212/154 , G06F2212/60 , G06F2212/6024 , G06F2212/62 , G06F2212/651 , G06F2212/657
Abstract: A data processing network includes a network of devices addressable via a system address space, the network including a computing device configured to execute an application in a virtual address space. A virtual-to-system address translation circuit is configured to translate a virtual address to a system address. A memory node controller has a first interface to a data resource addressable via a physical address space, a second interface to the computing device, and a system-to-physical address translation circuit, configured to translate a system address in the system address space to a corresponding physical address in the physical address space of the data resource. The virtual-to-system mapping may be a range table buffer configured to retrieve a range table entry comprising an offset address of a range together with a virtual address base and an indicator of the extent of the range.
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公开(公告)号：US20180150321A1
公开(公告)日：2018-05-31
申请号：US15361819
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Curtis Glenn DUNHAM , Jonathan Curtis BEARD , Roxana RUSITORU
CPC classification number: G06F9/4881 , G06F9/461 , G06F9/4843 , G06F12/0831
Abstract: Data processing apparatus comprises a group of two or more processing elements configured to execute processing instructions of a program task; the processing elements being configured to provide context data relating to a program task following execution of that program task by that processing element; and to receive context data, provided by that processing element or another processing element, at resumption of execution of a program task; in which a next processing element of the group to execute a program task is configured to receive a first subset of the context data from a previous processing element to execute that program task and to start to execute the program task using the first subset of the context data; and in which the next processing element is configured to receive one or more items of a second, remaining, subset of the context data during execution of the program task by that processing element.
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Patent Agency Ranking
公开(公告)号：US20200034230A1
公开(公告)日：2020-01-30
申请号：US16043975
申请日：2018-07-24
Applicant: Arm Limited
Inventor： Reiley JEYAPAUL , Roxana RUSITORU , Jonathan Curtis BEARD
Abstract: A memory system for a data processing apparatus includes a fault management unit, a memory controller (such as a memory management unit or memory node controller), and one or more storage devices accessible via the memory controller and configured for storing critical data. The fault management unit detects and corrects a fault in the stored critical data, a storage device or the memory controller. A data fault may be corrected using a copy of the data, or an error correction code, for example. A level of failure protection for the critical data, such as a number of copies, an error correction code or a storage location in the one or more storage devices, is determined dependent upon a failure characteristic of the device. A failure characteristic, such as an error rate, may be monitored and updated dynamically.
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公开(公告)号：US20230367676A1
公开(公告)日：2023-11-16
申请号：US17742875
申请日：2022-05-12
Applicant: Arm Limited
Inventor： Reiley JEYAPAUL , Roxana RUSITORU , Jonathan Curtis BEARD , Kar-Lik Kasim WONG
CPC classification number: G06F11/1407 , G06F8/433
Abstract: An apparatus comprises at least one processor to execute software processes, a memory system to store data for access by the at least one processor, and checkpointing circuitry to trigger saving, to the memory system, of checkpoints of context state associated with at least one software process executed by the at least one processor. The saving of checkpoints is a background process performed by the checkpointing circuitry in the background of execution of the software processes by the at least one processor.
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公开(公告)号：US20180150322A1
公开(公告)日：2018-05-31
申请号：US15361871
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Curtis Glenn DUNHAM , Jonathan Curtis BEARD , Roxana RUSITORU
Abstract: Data processing apparatus comprises one or more interconnected processing elements each configured to execute processing instructions of a program task; coherent memory circuitry storing one or more copies of data accessible by each of the processing elements, so that data written to a memory address in the coherent memory circuitry by one processing element is consistent with data read from that memory address in the coherent memory circuitry by another of the processing elements; the coherent memory circuitry comprising a memory region to store data, accessible by the processing elements, defining one or more attributes of a program task and context data associated with a most recent instance of execution of that program task; the apparatus comprising scheduling circuitry to schedule execution of a task by a processing element in response to the one or more attributes defined by data stored in the memory region corresponding to that task; and each processing element which executes a program task is configured to modify one or more of the attributes corresponding to that program task in response to execution of that program task.
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公开(公告)号：US20210306414A1
公开(公告)日：2021-09-30
申请号：US16828207
申请日：2020-03-24
Applicant: Arm Limited
Inventor： Jonathan Curtis BEARD , Jamshed JALAL , Curtis Glenn DUNHAM , Roxana RUSITORU
Abstract: Circuitry comprises a set of data handling nodes comprising: two or more master nodes each having respective storage circuitry to hold copies of data items from a main memory, each copy of a data item being associated with indicator information to indicate a coherency state of the respective copy, the indicator information being configured to indicate at least whether that copy has been updated more recently than the data item held by the main memory; a home node to serialise data access operations and to control coherency amongst data items held by the set of data handling nodes so that data written to a memory address is consistent with data read from that memory address in response to a subsequent access request; and one or more slave nodes including the main memory; in which: a requesting node of the set of data handling nodes is configured to communicate a conditional request to a target node of the set of data handling nodes in respect of a copy of a given data item at a given memory address, the conditional request being associated with an execution condition and being a request that the copy of the given data item is written to a destination node of the data handling nodes; and the target node is configured, in response to the conditional request: (i) when the outcome of the execution condition is successful, to write the data item to the destination node and to communicate a completion-success indicator to the requesting node; and (ii) when the outcome of the execution condition is a failure, to communicate a completion-failure indicator to the requesting node.
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公开(公告)号：US20180150315A1
公开(公告)日：2018-05-31
申请号：US15361770
申请日：2016-11-28
Applicant: ARM Limited
Inventor： Curtis Glenn DUNHAM , Jonathan Curtis BEARD , Roxana RUSITORU
Abstract: Data processing apparatus comprises one or more interconnected processing elements; each processing element being configured to execute processing instructions of program tasks; each processing element being configured to save context data relating to a program task following execution of that program task by that processing element; and to load context data, previously saved by that processing element or another of the processing elements, at resumption of execution of a program task; each processing element having respective associated format definition data to define one or more sets of data items for inclusion in the context data; the apparatus comprising format selection circuitry to communicate the format definition data of each of the processing elements with others of the processing elements and to determine, in response to the format definition data for each of the processing elements, a common set of data items for inclusion in the context data.
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