公开(公告)号：US10249577B2

公开(公告)日：2019-04-02

申请号：US15499647

申请日：2017-04-27

Applicant: ASM IP Holding B.V.

Inventor： Choong Man Lee ,  Yong Min Yoo ,  Young Jae Kim ,  Seung Ju Chun ,  Sun Ja Kim

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

公开(公告)号：US20170338192A1

公开(公告)日：2017-11-23

申请号：US15499647

申请日：2017-04-27

Applicant: ASM IP Holding B.V.

Inventor： Choong Man Lee ,  Yong Min Yoo ,  Young Jae Kim ,  Seung Ju Chun ,  Sun Ja Kim

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/564 ,  H01L21/02074 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.