公开(公告)号：US10381226B2

公开(公告)日：2019-08-13

申请号：US15662107

申请日：2017-07-27

Applicant: ASM IP Holding B.V.

Inventor： Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/3065 ,  H01L21/3105

Abstract: A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.

公开(公告)号：US10134757B2

公开(公告)日：2018-11-20

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US20180130701A1

公开(公告)日：2018-05-10

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US10438965B2

公开(公告)日：2019-10-08

申请号：US15798150

申请日：2017-10-30

Applicant: ASM IP Holding B.V.

Inventor： Young Jae Kim ,  Seung Woo Choi ,  Yong Min Yoo

IPC: H01L27/11582 ,  H01L21/225 ,  H01L21/28

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

公开(公告)号：US20180033625A1

公开(公告)日：2018-02-01

申请号：US15662107

申请日：2017-07-27

Applicant: ASM IP Holding B.V.

Inventor： Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim

IPC: H01L21/225 ,  H01L21/306 ,  H01L21/3105 ,  H01L21/3065

CPC classification number: H01L21/225 ,  H01L21/2255 ,  H01L21/30604 ,  H01L21/3065 ,  H01L21/31053

Abstract: A method of processing a substrate to enable selective doping without a photolithography process is provided. The method includes forming a diffusion barrier on the substrate having a patterned structure using plasma deposition method, removing the diffusion barrier except for part of the diffusion barrier using wet etching, forming a diffusion source layer on the patterned structure and the part of the diffusion barrier, and applying energy to the diffusion source layer.

公开(公告)号：US20170338192A1

公开(公告)日：2017-11-23

申请号：US15499647

申请日：2017-04-27

Applicant: ASM IP Holding B.V.

Inventor： Choong Man Lee ,  Yong Min Yoo ,  Young Jae Kim ,  Seung Ju Chun ,  Sun Ja Kim

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/564 ,  H01L21/02074 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

公开(公告)号：US20160181273A1

公开(公告)日：2016-06-23

申请号：US14938180

申请日：2015-11-11

Applicant: ASM IP Holding B.V.

Inventor： Young Jae Kim ,  Seung Woo Choi ,  Yong Min Yoo

IPC: H01L27/115 ,  H01L29/04

CPC classification number: H01L27/11582 ,  H01L21/2255 ,  H01L21/28282

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-demensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

Abstract translation: 公开了一种半导体器件及其制造方法。 根据根据本发明的示例性实施例的半导体器件及其制造方法，在掺杂剂源层通过等离子体增强原子层沉积（均匀地沉积在具有3维垂直结构的器件的沟道层上之后） PEALD）方法，将沉积的掺杂剂源层进行热处理，使得掺杂剂扩散到沟道层中以用作电荷载流子，从而防止沟道层中的电荷减小。 根据本发明的示例性实施例，可以通过在沟道层和掺杂剂源层之间形成势垒层来控制掺杂剂的扩散速度和浓度。

公开(公告)号：US10249577B2

公开(公告)日：2019-04-02

申请号：US15499647

申请日：2017-04-27

Applicant: ASM IP Holding B.V.

Inventor： Choong Man Lee ,  Yong Min Yoo ,  Young Jae Kim ,  Seung Ju Chun ,  Sun Ja Kim

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

公开(公告)号：US20180069019A1

公开(公告)日：2018-03-08

申请号：US15798150

申请日：2017-10-30

Applicant: ASM IP Holding B.V.

Inventor： Young Jae Kim ,  Seung Woo Choi ,  Yong Min Yoo

IPC: H01L27/11582 ,  H01L21/225 ,  H01L21/28

CPC classification number: H01L27/11582 ,  H01L21/2255 ,  H01L29/40117

Abstract: Disclosed are a semiconductor device and a manufacturing method thereof. According to the semiconductor device and the manufacturing method thereof according to exemplary embodiments of the present invention, after the dopant source layer is uniformly deposited on a channel layer of the device with the 3-dimensional vertical structure by the plasma-enhanced atomic layer deposition (PEALD) method, the deposited dopant source layer is heat-treated so that the dopants are diffused into the channel layer to function as charge carriers, thereby preventing the charges in the channel layer from being reduced. According to the exemplary embodiments of the present invention, the diffusion speed and concentration of the dopant may be controlled by forming the barrier layer between the channel layer and the dopant source layer.

公开(公告)号：US20190081072A1

公开(公告)日：2019-03-14

申请号：US16188690

申请日：2018-11-13

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/115 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/1157

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.