公开(公告)号：US10249577B2

公开(公告)日：2019-04-02

申请号：US15499647

申请日：2017-04-27

Applicant: ASM IP Holding B.V.

Inventor： Choong Man Lee ,  Yong Min Yoo ,  Young Jae Kim ,  Seung Ju Chun ,  Sun Ja Kim

IPC: H01L21/4763 ,  H01L23/00 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/522

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

公开(公告)号：US20170338192A1

公开(公告)日：2017-11-23

申请号：US15499647

申请日：2017-04-27

Applicant: ASM IP Holding B.V.

Inventor： Choong Man Lee ,  Yong Min Yoo ,  Young Jae Kim ,  Seung Ju Chun ,  Sun Ja Kim

IPC: H01L23/00 ,  H01L21/02 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522

CPC classification number: H01L23/564 ,  H01L21/02074 ,  H01L21/0217 ,  H01L21/02178 ,  H01L21/02211 ,  H01L21/02219 ,  H01L21/02274 ,  H01L21/0228 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/5226 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor manufacturing method includes depositing a low-k dielectric layer, forming a trench in the low-k dielectric layer, forming a barrier layer in the trench, filling a metal on the barrier layer, planarizing the metal, and forming a capping layer on the planarized metal, wherein the capping layer includes at least two layers.

公开(公告)号：US10134757B2

公开(公告)日：2018-11-20

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/115 ,  H01L21/311 ,  H01L21/768 ,  H01L23/532 ,  H01L23/522 ,  H01L23/528 ,  H01L27/11582 ,  H01L27/1157 ,  H01L27/11556

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US20180130701A1

公开(公告)日：2018-05-10

申请号：US15640239

申请日：2017-06-30

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L27/11582 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76829 ,  H01L21/76877 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76892 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11575

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US20190081072A1

公开(公告)日：2019-03-14

申请号：US16188690

申请日：2018-11-13

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L23/532 ,  H01L27/115 ,  H01L23/522 ,  H01L21/768 ,  H01L21/311 ,  H01L27/11556 ,  H01L27/1157

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.

公开(公告)号：US20190035810A1

公开(公告)日：2019-01-31

申请号：US16147047

申请日：2018-09-28

Applicant: ASM IP Holding B.V.

Inventor： Seung Ju Chun ,  Yong Min Yoo ,  Jong Wan Choi ,  Young Jae Kim ,  Sun Ja Kim ,  Wan Gyu Lim ,  Yoon Ki Min ,  Hae Jin Lee ,  Tae Hee Yoo

IPC: H01L27/11582 ,  H01L23/522 ,  H01L27/1157 ,  H01L27/11556 ,  H01L27/115 ,  H01L23/532 ,  H01L23/528 ,  H01L21/311 ,  H01L21/768 ,  H01L27/11575

Abstract: A method of processing a substrate by omitting a photolithographic process is disclosed. The method includes forming at least one layer on a stepped structure having an upper surface, a lower surface, and a side surface that connects the upper surface to the lower surface, selectively densifying portions of the at least one layer respectively on the upper surface and the lower surface via asymmetric plasma application, and performing an isotropic etching process on the at least one layer. During the isotropic etching process, the portion of the at least one layer formed on the upper surface is separated from the portion of the at least one layer formed on the lower surface.