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公开(公告)号：US20240232116A1
公开(公告)日：2024-07-11
申请号：US18312582
申请日：2023-05-04
发明人： Po-Wei Huang , Chih-Chiang Mao
CPC分类号： G06F13/4068 , G06F15/7839 , G06F2213/0016 , G06F2213/0042
摘要： A baseboard management control device is provided. The baseboard management control device includes an input and output device and a baseboard management controller. The input and output device includes a sensing device. The sensing device is coupled to multiple input pins and multiple output pins to sense and write the target data, respectively. The baseboard management controller includes a storage device and a main processor. The storage device is configured to pre-store the target data. The main processor is coupled to the storage device and reads the target data in the storage device according to a predetermined cycle. The baseboard management controller and the input and output device are respectively located on different circuit boards.
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公开(公告)号：US11615048B2
公开(公告)日：2023-03-28
申请号：US17542501
申请日：2021-12-06
发明人： Hung-Ming Lin , Chih-Chiang Mao
IPC分类号： G06F13/42
摘要： An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.
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公开(公告)号：US20220286155A1
公开(公告)日：2022-09-08
申请号：US17229832
申请日：2021-04-13
发明人： Hung-Ming Lin , Chih-Chiang Mao
IPC分类号： H04B1/38
摘要： A signal transceiving system and a signal receiver thereof are provided. The signal transceiving system includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. The comparator compares, in a first mode, the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder generates, in the first mode, at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value which is a serial signal and the instruction signal to a signal receiver.
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公开(公告)号：US11664792B1
公开(公告)日：2023-05-30
申请号：US17830365
申请日：2022-06-02
发明人： Chin-Ting Kuo , Chih-Chiang Mao
IPC分类号： H03K5/135 , H03K19/003 , H03K19/20
CPC分类号： H03K5/135 , H03K19/003 , H03K19/20
摘要： An electronic device and data transmission protection device thereof are provided. The data transmission protection device includes an input clock signal detector and a control signal generator. The input clock signal detector receives a reference clock signal, and detects a frequency of an input clock signal provided by a host end according to the reference clock signal, and frequencies of the reference clock signal and the input clock signal are different. The control signal generator enables a generated control signal when the frequency of the input clock signal is larger than a safety setting value. The control signal is used to disable the host end to perform a data accessing operation on a protected circuit.
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公开(公告)号：US20220283979A1
公开(公告)日：2022-09-08
申请号：US17542501
申请日：2021-12-06
发明人： Hung-Ming Lin , Chih-Chiang Mao
IPC分类号： G06F13/42
摘要： An adaptive serial general-purpose input output (ASGPIO) interface and a signal receiver thereof suitable for a secure control module (SCM) are provided. The ASGPIO interface includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. In a first mode, the comparator compares the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder, in the first mode, generates at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value as a serial signal and the instruction signal to a signal receiver.
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公开(公告)号：US20240345640A1
公开(公告)日：2024-10-17
申请号：US18481990
申请日：2023-10-05
发明人： Shih-Fang Chen , Chin-Ting Kuo , Chia-Wei Wang , Chih-Chiang Mao
IPC分类号： G06F1/24
CPC分类号： G06F1/24
摘要： Embodiments of the disclosure provide a method for resetting a processor and a computer device. The method includes: obtaining an image file corresponding to a coprocessor by a first component of the computer device, and loading the image file into a reference space in a RAM by the first component; loading the image file stored in the reference space into a specific space corresponding to the coprocessor by a second component of the computer device and validating the image file stored in the specific space by the second component in response to determining that the coprocessor needs to be reset; and resetting the coprocessor by the second component based on the image file stored in the specific space in response to the second component determining that the image file stored in the specific space is valid.
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公开(公告)号：US20240126928A1
公开(公告)日：2024-04-18
申请号：US18073577
申请日：2022-12-02
发明人： Chin-Ting Kuo , Chih-Chiang Mao
IPC分类号： G06F21/64 , G06F9/4401 , H04L9/00 , H04L9/08 , H04L9/32
CPC分类号： G06F21/64 , G06F9/4401 , H04L9/0825 , H04L9/3247 , H04L9/50
摘要： A data security verification method and an electronic apparatus are provided. In the data security verification method, when the electronic apparatus is powered on, a verification circuit verifies integrity of an executable image in a storage device. If verification fails, the verification circuit stops a host processor from executing the executable image. If the verification is successful, the verification circuit releases a host reset, and a processor reads and executes the executable image. When the processor reads the executable image, the verification circuit re-verifies the executable image, and the processor executes the executable image according to a verification result.
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公开(公告)号：US11502712B2
公开(公告)日：2022-11-15
申请号：US17229832
申请日：2021-04-13
发明人： Hung-Ming Lin , Chih-Chiang Mao
IPC分类号： H04B1/38
摘要： A signal transceiving system and a signal receiver thereof are provided. The signal transceiving system includes a signal transmitter. The signal transmitter includes a first data buffer, a comparator, and an encoder. The first data buffer receives transmitted data and provides previously transmitted data. The comparator receives currently transmitted data and receives the previously transmitted data. The comparator compares, in a first mode, the previously transmitted data with the currently transmitted data to generate a data variation information. The encoder generates, in the first mode, at least one index value and a corresponding instruction signal according to the data variation information. The signal transmitter sends the at least one index value which is a serial signal and the instruction signal to a signal receiver.
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