公开(公告)号：US12176065B2

公开(公告)日：2024-12-24

申请号：US17849197

申请日：2022-06-24

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Xuan Chen ,  Chih-Hua Hsu ,  Pradeep Jayaraman ,  Abdussalam Aburwein

IPC: G11C7/22 ,  G11C5/02 ,  G11C7/10 ,  G11C8/18

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.

公开(公告)号：US10530325B1

公开(公告)日：2020-01-07

申请号：US16118054

申请日：2018-08-30

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Dean E. Gonzales ,  Xuan Chen ,  Jeffrey Cooper ,  Milam Paraschou

IPC: H04B3/00 ,  H03H7/38 ,  H03M9/00 ,  H04L25/02 ,  H02H9/04

Abstract: Systems, apparatuses, and methods for performing efficient data transfer in a computing system are disclosed. A computing system includes multiple transmitters sending singled-ended data signals to multiple receivers. A receiver includes multiple series inductors moved from a signal path to sampling circuitry to a termination path used for impedance matching. The removed direct current (DC) resistances of the inductors in the signal path reduces signal attenuation. The termination path has alternating current (AC) reactances of the inductors, which provide a frequency-dependent termination impedance. This termination impedance provides a positive reflection coefficient for high operating frequencies, which boosts the input signal being received by the sampling circuitry.

公开(公告)号：US20230280906A1

公开(公告)日：2023-09-07

申请号：US17981982

申请日：2022-11-07

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Xuan Chen ,  Ross V. La Fetra ,  Michael John Litt

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0673 ,  G06F3/0629

Abstract: A memory package includes first, second, third, and fourth channels arranged consecutively in a clockwise direction on the memory package, each of the first, second, third, and fourth channels having access circuitry and memory arrays. In a first mode, the first channel controls access to the memory arrays in the second channel and the fourth channel controls access to the memory arrays in the third channel.

公开(公告)号：US20230420018A1

公开(公告)日：2023-12-28

申请号：US17849197

申请日：2022-06-24

Applicant: ATI Technologies ULC ,  Advanced Micro Devices, Inc.

Inventor： Xuan Chen ,  Chih-Hua Hsu ,  Pradeep Jayaraman ,  Abdussalam Aburwein

IPC: G11C7/22 ,  G11C7/10 ,  G11C8/18 ,  G11C5/02

CPC classification number: G11C7/222 ,  G11C7/1063 ,  G11C7/109 ,  G11C8/18 ,  G11C5/025

Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.