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公开(公告)号：US20230420018A1
公开(公告)日：2023-12-28
申请号：US17849197
申请日：2022-06-24
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Xuan Chen , Chih-Hua Hsu , Pradeep Jayaraman , Abdussalam Aburwein
CPC classification number: G11C7/222 , G11C7/1063 , G11C7/109 , G11C8/18 , G11C5/025
Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.
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公开(公告)号：US12028190B1
公开(公告)日：2024-07-02
申请号：US18086960
申请日：2022-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Pradeep Jayaraman , Karthik Gopalakrishnan , Andrew Egli
CPC classification number: H04L25/03038 , H04L25/4917 , H04L2025/03471
Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.
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公开(公告)号：US12176065B2
公开(公告)日：2024-12-24
申请号：US17849197
申请日：2022-06-24
Applicant: ATI Technologies ULC , Advanced Micro Devices, Inc.
Inventor： Xuan Chen , Chih-Hua Hsu , Pradeep Jayaraman , Abdussalam Aburwein
Abstract: A data processor is for accessing a memory having a first pseudo channel and a second pseudo channel. The data processor includes at least one memory accessing agent, a memory controller, and a data fabric. The at least one memory accessing agent generates generating memory access requests including first memory access requests that access the memory. The memory controller provides memory commands to the memory in response to the first memory access requests. The data fabric routes the first memory access requests to a first downstream port in response to a corresponding first memory request accessing the first pseudo channel, and to a second downstream port in response to the corresponding first memory request accessing the second pseudo channel. The memory controller has first and second upstream ports coupled to the first and second downstream ports of the data fabric, respectively, and a downstream port coupled to the memory.
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公开(公告)号：US20240214246A1
公开(公告)日：2024-06-27
申请号：US18086960
申请日：2022-12-22
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Pradeep Jayaraman , Karthik Gopalakrishnan , Andrew Egli
CPC classification number: H04L25/03038 , H04L25/4917 , H04L2025/03471
Abstract: A driver circuit includes a feed-forward equalization (FFE) circuit. The FFE circuit receives a plurality of pulse-amplitude modulation (PAM) symbol values to be transmitted at one of multiple PAM levels. The FFE circuit includes a first partial lookup table, one or more additional partial lookup tables, and an adder circuit. The first partial lookup table contains partial finite impulse-response (FIR) values and indexed based on a current PAM symbol value, a precursor PAM symbol value, and a postcursor PAM symbol value. The one or more additional partial lookup tables each contain partial FIR values and indexed based on a respective additional one or more of the PAM symbol values. The adder circuit adds results of lookups from the first partial lookup table and the additional partial lookup tables to produce an output value.
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公开(公告)号：US20240143007A1
公开(公告)日：2024-05-02
申请号：US17977289
申请日：2022-10-31
Applicant: Advanced Micro Devices, Inc. , ATI Technologies ULC
Inventor： Achal Kathuria , Tom Moiannou , Pradeep Jayaraman , Karthik Gopalakrishnan
CPC classification number: G05F1/575 , G05F1/565 , H03F3/45192
Abstract: A voltage regulator includes an input power supply node, an output regulated power supply node, a flipped voltage follower circuit, and a compensation capacitor. The flipped voltage follower circuit includes an output transistor configured as a common-source amplifier circuit. A source terminal of the output transistor is coupled to the input power supply node and a drain terminal of the output transistor is coupled to the output regulated power supply node. The flipped voltage follower circuit includes a folded cascode feedback circuit. The folded cascode feedback circuit includes a folding node. The folded cascode feedback circuit is configured to receive an output regulated voltage on the output regulated power supply node and to provide a feedback signal to a gate terminal of the output transistor. The compensation capacitor is coupled to the output regulated power supply node and the folding node.
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Patent Agency Ranking
公开(公告)号：US20240111618A1
公开(公告)日：2024-04-04
申请号：US17956542
申请日：2022-09-29
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron D. Willey , Karthik Gopalakrishnan , Pradeep Jayaraman , Ramon Mangaser
IPC: G06F11/07
CPC classification number: G06F11/079 , G06F11/073
Abstract: A method for receiving a multi-level error signal having more than two logic levels includes oversampling the multi-level error signal to provide sampled symbols, wherein a first level of the multi-level error signal indicates no error, and second and third levels of the multi-level error signal indicate first and second error conditions, respectively. The sampled signals are de-serialized to provide sets of symbols. A start of a symbol period is determined in response to detecting that a given sample is different from a prior sample, and the prior sample indicates no error. The sets of symbols are filtered to provide corresponding output symbols based on the start.
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公开(公告)号：US11909404B1
公开(公告)日：2024-02-20
申请号：US18079252
申请日：2022-12-12
Applicant: Advanced Micro Devices, Inc.
Inventor： Andy Huei Chu , Karthik Gopalakrishnan , Pradeep Jayaraman
CPC classification number: H03L7/0818 , H03L7/087 , H03L7/189
Abstract: A clocking circuit is provided using a master delay-locked loop (DLL) and a slave DLL. A master DLL code indicates a delay adjustment made at a master DLL. A delay of a slave DLL is adjusted based on the master DLL code. A replica phase detector at the slave DLL is temporarily enabled during an interface idle period. A slave DLL code is determined, and a configuration value is determined based on the slave DLL code to the master DLL code. The replica phase detector is then disabled.
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公开(公告)号：US20230141595A1
公开(公告)日：2023-05-11
申请号：US17855066
申请日：2022-06-30
Applicant: Advanced Micro Devices, Inc.
Inventor： Aaron D Willey , Karthik Gopalakrishnan , Pradeep Jayaraman
IPC: G06F1/08 , G11C11/4076
CPC classification number: G06F1/08 , G11C11/4076 , G11C11/406
Abstract: A data processing system includes a data processor coupled to a memory. The data processor includes a reference clock generation circuit for providing a reference clock signal, a first delay circuit for delaying the reference clock signal by a first amount to provide a command and address signal, a second delay circuit for delaying the reference clock signal by a second amount to provide a read data signal, a calibration circuit for determining current values of the first and second amounts, and a compensation circuit for calculating drifts in the first and second amounts based on a measured temperature change, at least one voltage sensitivity coefficient, and at least one temperature sensitivity coefficient, and for updating the first and second amounts according to the drifts.
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公开(公告)号：US12101135B2
公开(公告)日：2024-09-24
申请号：US18243243
申请日：2023-09-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Ramon Mangaser , Karthik Gopalakrishnan , Andy Huei Chu , Pradeep Jayaraman
Abstract: An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the second terminal and receives the power supply voltage. The reference voltage generation circuit is operable to form the shared reference voltage by mixing noise from the power supply voltage and noise from the second terminal.
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公开(公告)号：US20230421203A1
公开(公告)日：2023-12-28
申请号：US18243243
申请日：2023-09-07
Applicant: Advanced Micro Devices, Inc.
Inventor： Ramon Mangaser , Karthik Gopalakrishnan , Andy Huei Chu , Pradeep Jayaraman
Abstract: An integrated circuit includes a first terminal for receiving a data signal, a second terminal for receiving an external reference voltage, a receiver, and a reference voltage generation circuit. The receiver is powered by a power supply voltage with respect to ground and has a first input coupled to the first terminal, a second input for receiving a shared reference voltage, and an output for providing a data input signal. The reference voltage generation circuit is coupled to the second terminal and receives the power supply voltage. The reference voltage generation circuit is operable to form the shared reference voltage by mixing noise from the power supply voltage and noise from the second terminal.
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