公开(公告)号：US20220208145A1

公开(公告)日：2022-06-30

申请号：US17135346

申请日：2020-12-28

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. GLEN

IPC: G09G5/12 ,  G06F3/14

Abstract: A processing system synchronizes the display of a frame of video at an array of variable refresh rate (VRR) display modules of a display wall by dynamically adjusting a frequency and phase of the refresh rates of the VRR display modules via network protocols based on a selected master timing signal. The processing system selects a master timing signal and transmits the master timing signal to video processing units (VPUs) that render portions of the frame for display at the VRR display modules. Each VPU adjusts the frequency and phase of the VRR display modules for which it renders portions of the frame based on the master timing signal.

公开(公告)号：US20220108418A1

公开(公告)日：2022-04-07

申请号：US17060942

申请日：2020-10-01

Applicant: ATI TECHNOLOGIES ULC

Inventor： Anthony WL KOO ,  Syed Athar HUSSAIN ,  David I. J. GLEN

IPC: G06T1/20 ,  G09G3/36

Abstract: A display system receives first timing information prior to the display system entering a panel self-refresh (PSR) mode. The display system supports a range of refresh rates. Prior to the display system entering the PSR mode, first timing information indicating a first refresh rate that is lower than a maximum refresh rate supported by the display system is received by the display system. The display system then refreshes images at a second refresh rate that is less than or equal to the first refresh rate using a frame stored in a buffer prior to entering the PSR mode. In some cases, the processing unit also receives second timing information from the display system in response to initiating an exit from a panel self-refresh (PSR) mode. The second timing information indicates a current scanout line that is used to schedule transmission of a subsequent frame.

公开(公告)号：US20220210294A1

公开(公告)日：2022-06-30

申请号：US17138181

申请日：2020-12-30

Applicant: ATI TECHNOLOGIES ULC

Inventor： David I. J. GLEN

IPC: H04N5/04 ,  H03L7/099

Abstract: A processing system synchronizes the frequencies and phases of the display outputs of multiple video processing units (VPUs) by adjusting a local time base generated at each VPU to match a virtual global time base generated based on a network protocol and to synchronize video timing for the display outputs based on the virtual global time base.

公开(公告)号：US20210201852A1

公开(公告)日：2021-07-01

申请号：US16729795

申请日：2019-12-30

Applicant: ATI TECHNOLOGIES ULC

Inventor： Shu Key Keith LEE ,  David I. J. GLEN

IPC: G09G5/37 ,  G09G5/10

Abstract: A system includes a display monitor compatible with a video specification having a reference EOTF while exhibiting an actual EOTF that deviates from the reference EOFT. The system further includes a video source subsystem operable to determine an approximated EOTF representative of the actual EOTF based on user input received from a display of at least one test pattern to the user via the display monitor. The at least one test pattern is intended to elicit input from the user based on a visual inspection of the at least one test pattern by the user. The video source subsystem further is to convert color values of each video image of a stream of images to corresponding non-linear codewords based on the approximated EOTF, and transmit the codewords to the display monitor for display as display images representative of the video images.