公开(公告)号：US20240314267A1

公开(公告)日：2024-09-19

申请号：US18122315

申请日：2023-03-16

Applicant: ATI TECHNOLOGIES ULC

Inventor： Wing-Chi Chow

IPC: H04N7/00 ,  H04N7/01 ,  H04N7/025

CPC classification number: H04N7/007 ,  H04N7/0122 ,  H04N7/025

Abstract: In response to a video aspect ratio of a frame of video not matching an aspect ratio of a display panel of a display device, a source device of a processing system transmits only the frame to the display device and metadata indicating that the display device is to generate bars for letterboxing or pillarboxing. By generating the bars for letterboxing or pillarboxing at the display device instead of transmitting the bars from the source device to the display device or storing the bars at a frame buffer of the display device, the processing system conserves power and bandwidth.

公开(公告)号：US20240114150A1

公开(公告)日：2024-04-04

申请号：US17956601

申请日：2022-09-29

Applicant: ATI TECHNOLOGIES ULC

Inventor： Wing-Chi Chow ,  Yee Shun Chan ,  Nicholas James Chorney ,  Minghua Zhu

IPC: H04N19/172 ,  H04N21/43

CPC classification number: H04N19/172 ,  H04N21/4307

Abstract: A display processing device includes a display device interface and a processing unit. The processing is configured to transition at least a first component of the display processing system into a low-power state in response to an active region of a first video frame of a plurality of video frames having completed. A second component of the display processing device is configured to maintain a temporal count value corresponding to a current frame line of the plurality of video frames, and further to generate a first signal in response to the temporal count value corresponding to a first trigger value. The first signal causes the at least first component to transition out of the low-power state.

公开(公告)号：US20240112294A1

公开(公告)日：2024-04-04

申请号：US17957105

申请日：2022-09-30

Applicant: ATI TECHNOLOGIES ULC

Inventor： Jie Zhou ,  Wing-Chi Chow

IPC: G06T1/20 ,  G06T1/60 ,  G09G3/20 ,  G09G5/393

CPC classification number: G06T1/20 ,  G06T1/60 ,  G09G3/2096 ,  G09G5/393 ,  G09G2340/0414 ,  G09G2350/00 ,  G09G2360/12

Abstract: Techniques described herein allow multi-pass writeback processing of graphical frames (such as those having a high or ultrahigh resolution) to reduce bandwidth for display operations by, for example, splitting an input stream for processing by separate graphical pipelines as two or more spatially segmented portions. After receiving a graphical frame for processing, the graphical frame is spatially segmented into multiple portions. Each of the multiple portions is provided to a respective graphical pipeline of a plurality of graphical pipelines for processing. Each processed portion of the graphical frame is written substantially simultaneously to a corresponding portion of a system memory.

公开(公告)号：US11012094B2

公开(公告)日：2021-05-18

申请号：US16218581

申请日：2018-12-13

Applicant: ATI Technologies ULC

Inventor： Wing-Chi Chow

IPC: H03M13/15 ,  H03K19/21 ,  H03M13/00 ,  H03M13/11

Abstract: A programmable digital data encoder employs error correcting coding that uses Galois field multiplication logic wherein each bit of the product is produced by first applying pre-calculated mask values or mask values calculated via a processor executing code, and then applying an XOR circuit together with the mask bits from the pre-calculated or generated mask. In one example, a set of Galois field multipliers is used wherein each multiplier in the set includes a plurality of 2-bit input AND gate circuits and an m-bit input XOR gate circuit to produce a bit of the product. In one example, there are “m” mask values in a mask table wherein m is the symbol width. A different mask value is applied for each bit of the product. The mask values are each m-bits wide, and are stored, for example, in memory as a small look-up table with m m-bit entries or in m m-bit wide registers.