Dynamic control of latency tolerance reporting values

    公开(公告)号:US11552892B2

    公开(公告)日:2023-01-10

    申请号:US16557914

    申请日:2019-08-30

    IPC分类号: H04L47/10 G06F13/38 H04L47/24

    摘要: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.

    DYNAMIC CONTROL OF LATENCY TOLERANCE REPORTING VALUES

    公开(公告)号:US20210067451A1

    公开(公告)日:2021-03-04

    申请号:US16557914

    申请日:2019-08-30

    摘要: An endpoint processing device is provided for dynamically controlling latency tolerance reporting (LTR) values. The endpoint processing device comprises memory configured to store data and a processor. The processor is configured to execute a program and send, to a root point processing device via a peripheral component interconnect express (PCIe) link, a plurality of messages each comprising a memory access request and a LTR value indicating an amount of time to service the memory access request. The processor is also configured to, for each of the plurality of messages, determine, during execution of the program, a LTR value setting and set the LTR value as the determined LTR value setting.