公开(公告)号：US20160118009A1

公开(公告)日：2016-04-28

申请号：US14644692

申请日：2015-03-11

Applicant: AU Optronics Corporation

Inventor： Chih-Lung LIN ,  Yuan-Wei DU ,  Fu-Hsing CHEN ,  Chun-Da TU

IPC: G09G3/36 ,  H03K19/0185

CPC classification number: G09G3/3677 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0289 ,  H03K19/018507

Abstract: A display panel includes gate lines and a gate driver. The gate driver includes series coupled driving stages, in which an N-th driving stage of the series-coupled driving stages includes a driving unit and an input control unit. The driving unit transmits a first clock signal according to a control voltage level of a control node, so as to output a gate-driving signal. The input control unit transmits the gate-driving signal outputted from an (N−1)-th driving stage to the control nodes, so as to adjust the control voltage level to one of a first voltage level and a second voltage level. A predetermined time interval is present between a rising edge of the first clock signal and a falling edge of the second clock signal. During the predetermined time interval, the control voltage level is pulled to the first voltage level by the input control unit.

Abstract translation: 显示面板包括栅极线和栅极驱动器。 栅极驱动器包括串联耦合驱动级，其中串联耦合驱动级的第N驱动级包括驱动单元和输入控制单元。 驱动单元根据控制节点的控制电压电平发送第一时钟信号，以输出栅极驱动信号。 输入控制单元将从第（N-1）驱动级输出的栅极驱动信号发送到控制节点，以将控制电压电平调整为第一电压电平和第二电压电平之一。 在第一时钟信号的上升沿和第二时钟信号的下降沿之间存在预定的时间间隔。 在预定时间间隔期间，通过输入控制单元将控制电压电平拉至第一电压电平。

公开(公告)号：US20210225237A1

公开(公告)日：2021-07-22

申请号：US16765589

申请日：2018-12-26

Applicant: AU Optronics (Kunshan) Co., Ltd. ,  AU OPTRONICS CORPORATION

Inventor： TSI-HSUAN HSU ,  Manman LI ,  Chun-Da TU ,  FU LIANG LIN

IPC: G09G3/20 ,  G06F3/041

Abstract: The present invention of the embodiment provides a drive circuit, comprising a first group of drive circuits and a second group of drive circuits each having multiple stages of gate drive circuits connected in series, each stage of the gate drive circuits comprising a shift register outputting a first gate drive signal and a touch voltage stabilizing unit coupled to the shift register, the touch voltage stabilizing unit comprising a reference end electrically connected to a reference potential of the shift register, a first voltage stabilizing end electrically connected to the first gate drive signal, a second voltage stabilizing end outputting a second gate drive signal and a signal end electrically connected to a control signal, wherein the control signal disables the touch voltage stabilizing unit during a display period, and the control signal enables the touch voltage stabilizing unit during a touch period.

公开(公告)号：US20180315389A1

公开(公告)日：2018-11-01

申请号：US15953720

申请日：2018-04-16

Applicant: AU Optronics Corporation

Inventor： Kai-Wei HONG ,  Chun-Da TU ,  Ming-Hsien LEE ,  Chuang-Cheng YANG ,  Yi-Cheng LIN ,  Chun-Feng LIN

IPC: G09G3/36 ,  G11C19/28

CPC classification number: G09G3/3677 ,  G09G3/20 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/06 ,  G11C19/28 ,  G11C19/287

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

公开(公告)号：US20200090614A1

公开(公告)日：2020-03-19

申请号：US16690606

申请日：2019-11-21

Applicant: AU Optronics Corporation

Inventor： Kai-Wei HONG ,  Chun-Da TU ,  Ming-Hsien LEE ,  Chuang-Cheng YANG ,  Yi-Cheng LIN ,  Chun-Feng LIN

IPC: G09G3/36 ,  G11C19/28 ,  G09G3/20

Abstract: The present embodiment of the invention provides a gate driving circuit and a display apparatus using the gate driving circuit. The gate driving circuit has a plurality of shift registers, and each shift register includes a first output unit, a first pull-down unit, a second output unit, a second pull-down unit, a voltage coupling unit, and a voltage boosting unit. The first output unit is coupled to a node and a first output end. The second output unit is coupled to the node and a second output end. The first pull-down unit is coupled to the first output end and a reference potential. The second pull-down unit is coupled to the second output end and the reference potential. The voltage coupling unit is coupled between the node and the second output end. The voltage boosting unit is coupled to a preset potential, the first output end, and a node and a gate high potential of a shift register at a previous stage.

公开(公告)号：US20190043412A1

公开(公告)日：2019-02-07

申请号：US15864498

申请日：2018-01-08

Applicant: AU OPTRONICS CORPORATION

Inventor： Chuang-Cheng YANG ,  Chun-Feng LIN ,  Ming-Hsien LEE ,  Kai-Wei HONG ,  Chun-Da TU ,  Yi-Cheng LIN

IPC: G09G3/20

CPC classification number: G09G3/2092 ,  G09G3/3677 ,  G09G2310/0267 ,  G09G2310/0286 ,  G09G2310/0289 ,  G09G2310/08

Abstract: Provided is a gate driving circuit, coupled to a pixel array having multiple gate lines. The gate driving circuit includes multiple shift registers and multiple pull-up transistor, coupled to the pixel array and separately located on two opposite sides of the pixel array. Shift registers located on a same side are sequentially coupled to each other. An nth (n is a positive integer) pull-up transistor includes: a control end, coupled to a control end of a driving transistor of an (n−1)th shift register located on a same side as the nth pull-up transistor; a first end, used to receive a clock signal, where the clock signal is further input to an nth shift register of the shift registers located on an opposite side of the nth pull-up transistor; and a second end, coupled to an nth gate line of the pixel array and used to drive the nth gate line.