公开(公告)号：US10950636B2

公开(公告)日：2021-03-16

申请号：US16792291

申请日：2020-02-16

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Chin-Chuan Liu ,  Sung-Yu Su

IPC: H01L27/12 ,  G02F1/1333 ,  G02F1/1362 ,  H01L29/786 ,  G02F1/1368

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed. Another photolithography and etching process is performed by using said photo mask to form first to third openings and a via hole in the second interlayered insulation layer, wherein along a normal direction, the third opening and the first contact hole are overlapped, the via hole and the second contact hole are overlapped, the first opening and the third contact hole are overlapped, and the second opening and the fourth contact hole are overlapped.

公开(公告)号：US11776463B2

公开(公告)日：2023-10-03

申请号：US17717803

申请日：2022-04-11

Applicant: AU Optronics Corporation

Inventor： Shu-Hao Huang ,  Hsien-Chun Wang ,  Sung-Yu Su

IPC: G09G3/32

CPC classification number: G09G3/32 ,  G09G2300/0819

Abstract: A display device includes a light emitting unit, first and second capacitors, and first and second switches. The light emitting unit emits light according to a voltage level of a first node. A first terminal of the first capacitor is coupled to the first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the second node, and a second terminal of the first capacitor is coupled to the light emitting unit. A first terminal of the first switch is coupled to the first node, and a second terminal of the first switch is coupled to the light emitting unit. The second switch is configured to be turned on before the first switch is turned on, and a first terminal of the second switch is coupled to the first node.

公开(公告)号：US20210104192A1

公开(公告)日：2021-04-08

申请号：US16871066

申请日：2020-05-11

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Sung-Yu Su

IPC: G09G3/20

Abstract: A pixel array substrate including a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixels, a first multiplexer, a second multiplexer, a first connecting line and a second connecting line is provided. The substrate has a display area. The first signal lines are arranged on the substrate and define a first row region and a second row region of the display area. The pixels are arranged into a first pixel row and a second pixel row which are respectively disposed in the first row region and the second row region. The first multiplexer is disposed in the first row region and electrically connected to a part of the second signal lines. The second multiplexer is disposed in the second row region and electrically connected to another part of the second signal lines. The first connecting line is electrically connected to the first multiplexer. The second connecting line is electrically connected to the second multiplexer. The electrical resistivity of the first connecting line and the second connecting line is greater than the electrically resistivity of the first signal lines and the second signal lines.

公开(公告)号：US20200185432A1

公开(公告)日：2020-06-11

申请号：US16792291

申请日：2020-02-16

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Chin-Chuan Liu ,  Sung-Yu Su

IPC: H01L27/12 ,  H01L29/786 ,  G02F1/1368 ,  G02F1/1362 ,  G02F1/1333

Abstract: A method for fabricating an array substrate is provided. A gate insulation layer, first and second gates and a first interlayered insulation layer are formed on first and second active layers in order. A photolithography and etching process is performed by using a photo mask to form first to fourth contact holes in the gate insulation layer and the first interlayered insulation layer. First and second sources and first and second drains which are respectively connected to the first and second active layers through the first to fourth contact holes are formed. A second interlayered insulation layer is formed. Another photolithography and etching process is performed by using said photo mask to form first to third openings and a via hole in the second interlayered insulation layer, wherein along a normal direction, the third opening and the first contact hole are overlapped, the via hole and the second contact hole are overlapped, the first opening and the third contact hole are overlapped, and the second opening and the fourth contact hole are overlapped.

公开(公告)号：US11656704B2

公开(公告)日：2023-05-23

申请号：US17511610

申请日：2021-10-27

Applicant: AU Optronics Corporation

Inventor： Shu-Hao Huang ,  Sung-Yu Su

IPC: G06F3/041 ,  G06F3/044 ,  G09G3/20

CPC classification number: G06F3/0412 ,  G06F3/044 ,  G09G3/2092 ,  G09G2310/08

Abstract: A driving circuit includes a driving transistor, a capacitor, a reset circuit, a touch sensing electrode, a sensing circuit, and a read circuit. The capacitor is electrically coupled to a gate terminal of the driving transistor. The reset circuit is electrically coupled to the gate terminal of the driving transistor, and the reset circuit is configured to reset the voltage level of the gate terminal of the driving transistor. The sensing circuit is electrically coupled between the touch sensing electrode and the gate terminal of the driving transistor, and the sensing circuit is configured to transmit the voltage level of the touch sensing electrode to the gate terminal of the driving transistor. The read circuit is electrically coupled to the driving transistor, and the read circuit is configured to output a touch sensing signal according to the voltage level of the gate terminal of the driving transistor.

公开(公告)号：US11380235B2

公开(公告)日：2022-07-05

申请号：US16871066

申请日：2020-05-11

Applicant: Au Optronics Corporation

Inventor： Shu-Hao Huang ,  Sung-Yu Su

IPC: G09G3/20

Abstract: A pixel array substrate including a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of pixels, a first demultiplexer, a second demultiplexer, a first connecting line and a second connecting line is provided. The substrate has a display area. The first signal lines are arranged on the substrate and define a first row region and a second row region of the display area. The pixels are arranged into a first pixel row and a second pixel row which are respectively disposed in the first row region and the second row region. The first demultiplexer is disposed in the first row region and electrically connected to a part of the second signal lines. The second demultiplexer is disposed in the second row region and electrically connected to another part of the second signal lines. The first connecting line is electrically connected to the first demultiplexer. The second connecting line is electrically connected to the second demultiplexer. The electrical resistivity of the first connecting line and the second connecting line is greater than the electrically resistivity of the first signal lines and the second signal lines.

公开(公告)号：US11335248B1

公开(公告)日：2022-05-17

申请号：US17203792

申请日：2021-03-17

Applicant: AU Optronics Corporation

Inventor： Shu-Hao Huang ,  Hsien-Chun Wang ,  Sung-Yu Su

IPC: G09G3/32

Abstract: A display device includes a pixel driving circuit including a data writing unit, a light emitting unit and a compensation unit. The data writing unit includes first and second capacitors. A first terminal of the first capacitor is coupled to a first node, and a second terminal of the first capacitor is coupled to a second node. A first terminal of the second capacitor is coupled to the first node. The light emitting unit includes a first switch and a light emitting element. A control terminal of the first switch is coupled to the second node, and a first terminal of the first switch is coupled to a second terminal of the second capacitor. The compensation unit includes a second switch. The second switch is coupled to the second node and a second terminal of the first switch.

公开(公告)号：US10782814B2

公开(公告)日：2020-09-22

申请号：US16297735

申请日：2019-03-11

Applicant: Au Optronics Corporation

Inventor： Rong-Fu Lin ,  Chun-Wei Chang ,  Shu-Hao Huang ,  Sung-Yu Su ,  Jie-Chuan Huang ,  Yun-I Liu

IPC: G06F3/041 ,  G09G3/20

Abstract: A touch display panel includes a pixel array, a touch module, and a multiplexer circuit. The pixel array includes a plurality of pixels, a plurality of gate lines, and a plurality of source lines. The pixels are electrically coupled to the source lines and the gate lines. The touch module and the pixel array are overlapped. The multiplexer circuit is coupled between all of the source lines and a source driver and has a plurality of multiplexers. The multiplexers are respectively coupled to n source lines and respectively include a plurality of switches and a bypass trace. The switches are respectively coupled between the first source line to the (n−1)th source line of the n source lines and the source drivers. The bypass trace is coupled between the nth source line of the n source lines and the source driver.

公开(公告)号：US10699653B2

公开(公告)日：2020-06-30

申请号：US16119058

申请日：2018-08-31

Applicant: AU Optronics Corporation

Inventor： Dong-Hun Lim ,  Shu-Hao Huang ,  Chen-Feng Fan

IPC: G09G3/36 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/133

Abstract: A pixel circuit includes a first switch, a storage circuit, a second switch, and a liquid crystal capacitor. The first node of the first switch is configured to receive a data signal, and the second node of the first switch is coupled with a first node point. The storage circuit is coupled with the first node point, and configured to receive a common voltage. The first node of the second switch is coupled with the storage circuit, and the second node of the second switch is configured to receive a boost signal. The liquid crystal capacitor is coupled between the first node point and the storage circuit. In response to the first switch is conducted, the second switch is conducted, or in response to the second switch is conducted, the first switch is conducted.

公开(公告)号：US20200074946A1

公开(公告)日：2020-03-05

申请号：US16119058

申请日：2018-08-31

Applicant: AU Optronics Corporation

Inventor： Dong-Hun Lim ,  Shu-Hao Huang ,  Chen-Feng Fan

IPC: G09G3/36 ,  H01L27/12 ,  G02F1/1343 ,  G02F1/1362 ,  G02F1/1368 ,  G02F1/133

Abstract: A pixel circuit includes a first switch, a storage circuit, a second switch, and a liquid crystal capacitor. The first node of the first switch is configured to receive a data signal, and the second node of the first switch is coupled with a first node point. The storage circuit is coupled with the first node point, and configured to receive a common voltage. The first node of the second switch is coupled with the storage circuit, and the second node of the second switch is configured to receive a boost signal. The liquid crystal capacitor is coupled between the first node point and the storage circuit. In response to the first switch is conducted, the second switch is conducted, or in response to the second switch is conducted, the first switch is conducted.