公开(公告)号：US4758745A

公开(公告)日：1988-07-19

申请号：US909261

申请日：1986-09-19

申请人： Abbas Elgamal ,  Khaled A. El-Ayat ,  Amr Mohsen

发明人： Abbas Elgamal ,  Khaled A. El-Ayat ,  Amr Mohsen

IPC分类号： G01R31/3185 ,  H03K19/177 ,  H03K17/693

CPC分类号： H03K19/17748 ,  G01R31/318516 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/17736 ,  H03K19/17796

摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable elements situated at the intersection of any two segments to be connected. Sensing circuitry and wiring may be included to allow 100% observability of internal circuit nodes, such as module outputs, from an external pad interface.

摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 布线通道包括通过常开的可编程元件连接的布线段，所述可编程元件位于要连接的任何两个段的交点处。 可以包括感应电路和接线，以允许来自外部接口接口的内部电路节点（如模块输出）的100％可观察性。

公开(公告)号：US5600265A

公开(公告)日：1997-02-04

申请号：US575519

申请日：1995-12-20

申请人： Abbas El Gamal ,  Khaled A. El-Ayat ,  Amr Mohsen

发明人： Abbas El Gamal ,  Khaled A. El-Ayat ,  Amr Mohsen

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L25/00 ,  H03K19/177

CPC分类号： G01R31/2884 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17736

摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 接线通道包括通过常开可编程连接的接线段。 位于要连接的任何两个段的交点处的元素。

公开(公告)号：US5479113A

公开(公告)日：1995-12-26

申请号：US342735

申请日：1994-11-21

申请人： Abbas E. Gamal ,  Khaled A. El-Ayat ,  Amr Mohsen

发明人： Abbas E. Gamal ,  Khaled A. El-Ayat ,  Amr Mohsen

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L25/00 ,  H03K19/177 ,  H03K17/693

CPC分类号： G01R31/2884 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17736

摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过垂直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 接线通道包括通过常开可编程连接的接线段。 位于要连接的任何两个段的交点处的元素。

公开(公告)号：US5341267A

公开(公告)日：1994-08-23

申请号：US763964

申请日：1991-09-23

申请人： Ralph G. Whitten ,  Ta-Pen Guo ,  Amr Mohsen ,  Alan E. Comer

发明人： Ralph G. Whitten ,  Ta-Pen Guo ,  Amr Mohsen ,  Alan E. Comer

IPC分类号： H01L23/60 ,  H02H9/00 ,  H01H37/76

CPC分类号： H01L23/60 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A first passive ESD protection device for an electronic component in a microcircuit includes a fuse element shunting the component to be protected and includes a passive programming path from the outside of the microcircuit to the fuse element. A second passive ESD protection device is deactivatable and reactivatable and includes a first fuse element shunted by a second fuse element in series with a first antifuse element. Shunting the second fuse element with a third fuse element in series with a second antifuse element permits a second deactivation and reactivation to be performed. Additional deactivation/reactivation cycles may be permitted by providing additional series combinations of fuse elements and antifuse elements shunting the preceding fuse element. Combinations of the passive protection device and dual elements comprise ESD protection schemes which may be deactivated and activated multiple times.

摘要翻译： 用于微电路中的电子部件的第一无源ESD保护装置包括分流待保护的部件的熔丝元件，并且包括从微电路的外部到熔丝元件的无源编程路径。 第二无源ESD保护装置是可去激活的并且可再生的，并且包括由与第一反熔丝元件串联的第二熔丝元件分流的第一熔丝元件。 利用与第二反熔丝元件串联的第三熔丝元件来分流第二熔丝元件允许执行第二失活和重新激活。 可以通过提供分流前一个熔丝元件的熔丝元件和反熔丝元件的附加串联组合来允许附加的去激活/重新激活循环。 被动保护装置和双重元件的组合包括ESD保护方案，其可以被多次停用和激活。

公开(公告)号：US5432708A

公开(公告)日：1995-07-11

申请号：US958872

申请日：1992-10-08

申请人： Amr Mohsen

发明人： Amr Mohsen

IPC分类号： H01L23/525 ,  H01L23/538 ,  H01L25/065 ,  H01L27/118 ,  H03K19/177 ,  H03K17/693

CPC分类号： H01L27/11898 ,  H01L23/525 ,  H01L23/5382 ,  H01L25/0655 ,  H03K19/17704 ,  H01L2924/0002 ,  H01L2924/3011

摘要： A high I/O count integrated circuit is disposed on a semiconductor chip having opposing faces and comprises a plurality of functional circuit modules, each having inputs and at least one output having a first drive capability. A plurality of a first type of I/O nodes, each comprising a first conductive structure is disposed in a first I/O node array on the surface of a first one of the semiconductor chip faces. A plurality of a second type of I/O nodes, each comprising a first conductive structure is disposed on the first semiconductor chip face. An interconnect architecture comprising a plurality of conductors is superimposed on the functional circuit modules, the interconnect architecture comprises a plurality of interconnect conductors. Selected ones of the interconnect conductors are connectable to the inputs and at least one output of selected ones of the functional circuit modules by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to other selected ones of the interconnect conductors by user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the first I/O nodes by electrically programmable user-programmable interconnect elements. Selected ones of the interconnect conductors are connectable to the second I/O nodes by electrically programmable user-programmable interconnect elements.

摘要翻译： 高I ​​/ O计数集成电路设置在具有相对面的半导体芯片上，并且包括多个功能电路模块，每个具有输入和至少一个具有第一驱动能力的输出。 多个第一类型的I / O节点，每个包括第一导电结构，设置在第一I / O节点阵列中的第一个半导体芯片面的表面上。 每个包括第一导电结构的多个第二类型的I / O节点设置在第一半导体芯片面上。 包括多个导体的互连架构叠加在功能电路模块上，互连架构包括多个互连导体。 通过电可编程的用户可编程的互连元件，所选择的互连导体中的一些可连接到输入端和功能电路模块中的选定功能电路模块的至少一个输出端。 互连导体中的选定的导体可通过用户可编程的互连元件连接到互连导线中的其它选定的互连导体。 所选择的互连导体可通过电可编程用户可编程互连元件连接到第一I / O节点。 所选择的互连导体可通过电可编程的用户可编程互连元件连接到第二I / O节点。

公开(公告)号：US6160420A

公开(公告)日：2000-12-12

申请号：US754189

申请日：1996-11-12

申请人： Abbas El Gamal ,  Khaled A. El-Avat ,  Amr Mohsen

发明人： Abbas El Gamal ,  Khaled A. El-Avat ,  Amr Mohsen

IPC分类号： G01R31/28 ,  G01R31/3185 ,  H01L25/00 ,  H03K19/177

CPC分类号： G01R31/2884 ,  G01R31/318516 ,  G01R31/318519 ,  H03K19/17704 ,  H03K19/17736

摘要： A user-programmable interconnect architecture, which may be used for logic arrays for digital and analog system design, is disclosed. In one embodiment, a plurality of logic cells or modules in a matrix are connected by vertical and horizontal wiring channels. The wiring channels may in turn be programmed by the user to interconnect the various logic cells to implement the required logic function. The wiring channels comprise wiring segments connected by normally open programmable. Elements situated at the intersection of any two segments to be connected.

摘要翻译： 公开了可用于数字和模拟系统设计的逻辑阵列的用户可编程互连体系结构。 在一个实施例中，矩阵中的多个逻辑单元或模块通过竖直和水平布线通道连接。 接线通道可以由用户编程，以互连各种逻辑单元以实现所需的逻辑功能。 接线通道包括通过常开可编程连接的接线段。 位于要连接的任何两个段的交点处的元素。

公开(公告)号：US5451811A

公开(公告)日：1995-09-19

申请号：US260688

申请日：1994-06-16

申请人： Ralph G. Whitten ,  Amr Mohsen

发明人： Ralph G. Whitten ,  Amr Mohsen

IPC分类号： H01L23/525 ,  H01L27/02 ,  H01L23/48

CPC分类号： H01L23/5252 ,  H01L2924/0002 ,  H01L2924/09701 ,  H01L2924/3011

摘要： A user-programmable interconnect device includes a first lower electrode comprising a conductive material. A layer of dielectric material is disposed over the top surface of the lower conductor. An antifuse material, such as one or more layers of a dielectric material, amorphous silicon, or combinations of such materials, is located in an aperture in the dielectric material where the interconnect element of the present invention is to be formed. A second, upper electrode of conductive material is formed over the top of the antifuse material. A portion of the upper electrode located immediately above the antifuse material is fabricated as a fuse material. A passivation layer covers the second electrode and may have an aperture located therein at a location immediately above the antifuse and fuse material. Electrical connections to circuitry incorporating the interconnect element of the present invention are made to the lower and upper electrodes.

摘要翻译： 用户可编程互连装置包括包括导电材料的第一下电极。 介电材料层设置在下导体的顶表面上。 诸如介电材料的一层或多层，非晶硅或这种材料的组合的反熔丝材料位于要形成本发明的互连元件的电介质材料的孔中。 第二导电材料的上电极形成在反熔丝材料的顶部上。 位于反熔丝材料正上方的上部电极的一部分被制造为熔丝材料。 钝化层覆盖第二电极，并且可以在位于反熔丝和熔丝材料正上方的位置处具有孔。 与包含本发明的互连元件的电路的电连接被制成下电极和上电极。