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20 条记录 (耗时 0.028 秒)

    Cover instruction and asynchronous backing store switch
    1.
    发明授权
    Cover instruction and asynchronous backing store switch 失效
    封面指令和异步后备存储开关

    公开(公告)号：US6065114A

    公开(公告)日：2000-05-16

    申请号：US64091

    申请日：1998-04-21

    申请人： Achmed Rumi Zahir ,  Jonathan K. Ross ,  Carol Thompson ,  Cary Coutant ,  Prasad Raje ,  Sunil Saxena

    发明人： Achmed Rumi Zahir ,  Jonathan K. Ross ,  Carol Thompson ,  Cary Coutant ,  Prasad Raje ,  Sunil Saxena

    IPC分类号： G06F9/30 ,  G06F9/40 ,  G06F9/46 ,  G06F9/48

    CPC分类号： G06F9/4812 ,  G06F9/3009 ,  G06F9/30127 ,  G06F9/30134 ,  G06F9/4425 ,  G06F9/461

    摘要： A computer-implemented method of switching contexts in a processor is provided. The processor includes a register stack (RS) that has first and second portions. The processor includes a register stack engine (RSE) to exchange information, in one of instruction execution dependent and independent modes between the second portion and the storage area. The computer implemented method of switching contexts includes the following steps: It is determined whether an interrupt occurred; a first register (IFM) configured to store a content of a second register (CFM) is invalidated, the CFM is configured to store control information related to the first portion; it is determined whether an interrupt handler needs to access the RS; and if so, the IFM is validated, the content of the CFM is copied to the IFM, and RSE is caused to exchange information between both the first and second portions of the RS and the storage area. On return from interruption, if IFM is validated, CFM is restored from IFM else CFM remains unchanged. The COVER instruction enables lightweight interrupt handling in a processor with a Register Stack.

    摘要翻译： 提供了一种在处理器中切换上下文的计算机实现的方法。 处理器包括具有第一和第二部分的寄存器堆栈（RS）。 该处理器包括一个寄存器堆栈引擎（RSE），用于在第二部分和存储区域之间以指令执行相关和独立模式之一交换信息。 计算机实现的切换上下文的方法包括以下步骤：确定是否发生中断; 配置为存储第二寄存器（CFM）的内容的第一寄存器（IFM）无效，所述CFM被配置为存储与所述第一部分相关的控制信息; 确定中断处理程序是否需要访问RS; 如果是，则IFM被验证，CFM的内容被复制到IFM，并且使RSE在RS的第一和第二部分与存储区域之间交换信息。 从中断返回时，如果IFM被验证，则从IFM恢复CFM，否则CFM保持不变。 COVER指令在具有寄存器堆栈的处理器中实现轻量级中断处理。

    Automated creation and maintenance of programs to process internet form related submissions
    2.
    发明授权
    Automated creation and maintenance of programs to process internet form related submissions 有权
    自动创建和维护程序来处理互联网表单相关提交

    公开(公告)号：US07934149B1

    公开(公告)日：2011-04-26

    申请号：US09669594

    申请日：2000-09-26

    申请人： Prasad Raje

    发明人： Prasad Raje

    IPC分类号： G06F17/00 ,  G06F9/44

    CPC分类号： G06F17/243

    摘要： According to one aspect of the present invention, a method is provided in which a form is received from an author. A parsing function is performed to extract attribute information with respect to various form elements contained in the form. A user interface is presented to the author to allow the author to configure a set of actions that are to be performed in processing the submissions of the form.

    摘要翻译： 根据本发明的一个方面，提供了一种从作者接收表单的方法。 执行解析功能以提取关于形式中包含的各种形式元素的属性信息。 向作者呈现用户界面，以允许作者配置在处理表单提交时要执行的一组操作。

    Method for storing and decoding instructions for a microprocessor having a plurality of function units
    4.
    发明授权
    Method for storing and decoding instructions for a microprocessor having a plurality of function units 失效
    用于存储和解码具有多个功能单元的微处理器的指令的方法

    公开(公告)号：US5930508A

    公开(公告)日：1999-07-27

    申请号：US871128

    申请日：1997-06-09

    申请人： Paolo Faraboschi ,  Prasad Raje

    发明人： Paolo Faraboschi ,  Prasad Raje

    IPC分类号： G06F9/30 ,  G06F9/318 ,  G06F9/38 ,  G06F7/00

    CPC分类号： G06F9/3808 ,  G06F9/30152 ,  G06F9/30178 ,  G06F9/3816 ,  G06F9/3822 ,  G06F9/3885

    摘要： A method and apparatus for compacting VLIW instructions in a processor having multiple functional units and including a buffer for storing compacted instructions, wherein NOP codes are eliminated from the compacted instruction and each compacted instruction includes words which contain an operation code directing the operation of one of the functional units, a dispersal code, and a delimiter code, wherein an alignment circuit parses each compacted instruction from the buffer based upon the delimiter codes of the words and aligns the compacted instruction in an alignment buffer and a dispersal circuit transfers each word of the compacted instruction stored in the alignment buffer into at least one operational field of a dispersed instruction buffer which stores an executable instruction having an operational field corresponding to each one of the functional units. Another embodiment is also shown which interleaves the bits of a buffer, alignment circuit, alignment buffer, dispersal circuit and dispersed instruction buffer to reduce the circuit area required for expanding the compacted instruction.

    摘要翻译： 一种用于在具有多个功能单元的处理器中压缩VLIW指令的方法和装置，并且包括用于存储压缩指令的缓冲器，其中从压缩指令中消除NOP代码，并且每个压缩指令包括字，其包含指示操作代码 功能单元，分散代码和分隔符代码，其中对齐电路基于单词的定界符代码对缓冲器中的每个压缩指令进行解析，并将对准缓冲器中的压缩指令对准，并且扩散电路将每个单词 存储在对准缓冲器中的压缩指令到分散指令缓冲器的至少一个操作区域中，该分散指令缓冲器存储具有与每个功能单元相对应的操作区域的可执行指令。 还示出了另一个实施例，其交替缓冲器，对准电路，对准缓冲器，分散电路和分散指令缓冲器的位，以减少扩展压缩指令所需的电路面积。