公开(公告)号：US20060262779A1

公开(公告)日：2006-11-23

申请号：US10908597

申请日：2005-05-18

申请人： Adam Courchesne ,  Kenneth Goodnow ,  W. Harding ,  David Milton ,  Jason Norman ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

发明人： Adam Courchesne ,  Kenneth Goodnow ,  W. Harding ,  David Milton ,  Jason Norman ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

IPC分类号： H04L12/50

CPC分类号： G06F15/7825

摘要： A method and apparatus for providing communication between various cores located in an integrated circuit. The method and apparatus uses Hubs/Routers to facilitate and manage communication of data from/between the cores according to a specified methodology.

摘要翻译： 一种用于提供位于集成电路中的各种核心之间的通信的方法和装置。 该方法和装置使用集线器/路由器来根据指定的方法来促进和管理来自/在核心之间的数据的通信。

公开(公告)号：US20070204094A1

公开(公告)日：2007-08-30

申请号：US11276449

申请日：2006-02-28

申请人： W. Harding ,  David Milton ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

发明人： W. Harding ,  David Milton ,  Clarence Ogilvie ,  Jason Rotella ,  Paul Schanely ,  Sebastian Ventrone

IPC分类号： G06F13/00

CPC分类号： G06F13/14 ,  G06F13/362

摘要： A method and apparatus for transmitting data between cores residing in an integrated circuit. Data is transmitted by using hubs located between the cores and an arbiter. The arbiter maintains a table that contains all the valid combinations of routing paths between the cores.

摘要翻译： 一种用于在驻留在集成电路中的核之间传送数据的方法和装置。 通过使用位于核心和仲裁器之间的集线器来传输数据。 仲裁器维护一个表，其中包含核心之间路由路径的所有有效组合。

公开(公告)号：US20070025489A1

公开(公告)日：2007-02-01

申请号：US11161335

申请日：2005-07-29

申请人： David Milton ,  Jason Rotella

发明人： David Milton ,  Jason Rotella

IPC分类号： H03D3/24

CPC分类号： G06F1/12

摘要： A method and circuit for dynamically changing the frequency of clock signals. The method including: detecting an edge of a first clock signal operating at a first frequency using a second clock signal operating at a second frequency; detecting an edge of the second clock signal using the first clock signal; detecting coincident edges of the first and the second clock signals; and changing the second frequency to a third frequency different from the second frequency upon detection of the coincident edges.

摘要翻译： 一种用于动态改变时钟信号频率的方法和电路。 该方法包括：使用以第二频率操作的第二时钟信号来检测以第一频率工作的第一时钟信号的边沿; 使用所述第一时钟信号检测所述第二时钟信号的边沿; 检测第一和第二时钟信号的重合边缘; 以及在检测到所述重合边缘时将所述第二频率改变为与所述第二频率不同的第三频率。

公开(公告)号：US06509766B1

公开(公告)日：2003-01-21

申请号：US09999644

申请日：2001-10-26

申请人： Gerald Pomichter ,  Jason Rotella

发明人： Gerald Pomichter ,  Jason Rotella

IPC分类号： H03B1900

CPC分类号： G06F7/68 ,  H03K5/133 ,  H03K2005/00058

摘要： An adjustable clock multiplier circuit is disclosed which is believed to be of advantage for inexpensively and locally generating an adjustable high frequency clock, such as may be useful for built-in self test of an embedded memory element of a digital logic integrated circuit. The clock multiplier circuit uses a pulse generator of the monostable type to generate a pulse in response to the leading edge of an input clock signal. The pulse is delayed through a programmable delay circuit and then provided as a feedback input to the pulse generator. In such manner, an output clock signal comprised of a train of pulses is generated during a cycle of the input clock signal. A counter increments a count in response to pulses generated in this way. When the pulse count is too high, a limiter outputs an ADJUST DOWN signal which slows down the output cycle time of the clock multiplier. When the pulse count is too low, the limiter outputs an ADJUST UP signal which speeds up the output cycle time of the clock multiplier. The ADJUST DOWN/UP signals are preferably provided to a register which maintains and outputs a string of control signals for controlling a set of delay elements within a programmable delay circuit. The programmable delay circuit optionally includes a tap point multiplexer for varying the number of delay elements in the delay path, to provide greater range of frequency multiple and faster lock.

摘要翻译： 公开了一种可调节的时钟倍增器电路，其被认为对于廉价和本地生成可调节的高频时钟是有利的，例如可能对于数字逻辑集成电路的嵌入式存储器元件的内置自测试是有用的。 时钟倍频电路使用单稳态脉冲发生器响应于输入时钟信号的前沿产生脉冲。 脉冲通过可编程延迟电路延迟，然后作为反馈输入提供给脉冲发生器。 以这种方式，在输入时钟信号的周期期间产生由一串脉冲组成的输出时钟信号。 计数器响应于以这种方式产生的脉冲递增计数。 当脉冲数太高时，限幅器输出ADJUST DOWN信号，减慢时钟乘法器的输出周期时间。 当脉冲数太低时，限幅器输出一个ADJUST UP信号，可加快时钟倍频器的输出周期时间。 ADJUST DOWN / UP信号优选地被提供给寄存器，该寄存器保持并输出用于控制可编程延迟电路内的一组延迟元件的一串控制信号。 可编程延迟电路可选地包括用于改变延迟路径中的延迟元件的数量的分接点多路复用器，以提供更大范围的频率倍数和更快的锁定。

公开(公告)号：US06697277B2

公开(公告)日：2004-02-24

申请号：US10421963

申请日：2003-04-23

申请人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

发明人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

IPC分类号： G11C1500

CPC分类号： G11C29/50008 ,  G11C15/00 ,  G11C15/04 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5002

摘要： A match line circuit in a content addressable memory (CAM) has a match line coupled to a first pull-up device and a first pull-down device at a match node. The first pull-up device has selectively adjustable pull-up impedances associated with it. The match line circuit also includes a second pull-up device coupled to a second pull-down device at a float node, and an enabling signal for activating the match line circuit during a memory comparison operation. The enabling signal precharges the match node to a logic low level and the float node to a logic high level in between memory comparison operations.

摘要翻译： 内容可寻址存储器（CAM）中的匹配线路电路具有耦合到匹配节点处的第一上拉设备和第一下拉设备的匹配线。 第一上拉装置具有与其相关联的选择性可调的上拉阻抗。 匹配线电路还包括耦合到浮动节点处的第二下拉装置的第二上拉装置，以及用于在存储器比较操作期间激活匹配线电路的使能信号。 启用信号将匹配节点预充电到逻辑低电平，并将浮点节点在存储器比较操作之间进行逻辑高电平。

公开(公告)号：US06618279B2

公开(公告)日：2003-09-09

申请号：US09922893

申请日：2001-08-06

申请人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

发明人： Fred J. Towler ,  Reid A. Wistort ,  Jason Rotella

IPC分类号： G11C1500

CPC分类号： G11C29/50008 ,  G11C15/00 ,  G11C15/04 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5002

摘要： A method for determining a desired operating impedance for a computer memory circuit includes applying, to a reference circuit, a test impedance value to a reference circuit. The test impedance value is controlled by a binary count. A determination is made, based upon the applied test impedance value, whether the reference circuit is in either a first state or a second state. The binary count is incremented if the reference circuit is in the first state and decremented if the reference circuit is in the second state. A condition is determined in which the reference circuit oscillates between the first state and said second state, and a pair of binary count values is stored. The desired operating impedance for the computer memory circuit corresponds to the lower of the stored pair of binary count values.

摘要翻译： 一种用于确定计算机存储器电路的期望工作阻抗的方法包括将参考电路的测试阻抗值应用于参考电路。 测试阻抗值由二进制计数控制。 基于所应用的测试阻抗值，确定参考电路是处于第一状态还是第二状态。 如果参考电路处于第一状态，则二进制计数递增，如果参考电路处于第二状态则递减。 确定参考电路在第一状态和所述第二状态之间振荡的条件，并存储一对二进制计数值。 计算机存储器电路的期望工作阻抗对应于存储的一对二进制计数值中的较低者。

公开(公告)号：US20070226667A1

公开(公告)日：2007-09-27

申请号：US11277385

申请日：2006-03-24

申请人： Thomas Chadwick ,  Margaret Charlebois ,  David Hathaway ,  Jason Rotella ,  Douglas Stout ,  Ivan Wemple

发明人： Thomas Chadwick ,  Margaret Charlebois ,  David Hathaway ,  Jason Rotella ,  Douglas Stout ,  Ivan Wemple

IPC分类号： G06F17/50 ,  G06F9/45

CPC分类号： G06F17/5031

摘要： A method, system and computer program product for analyzing and modifying a static timing slack of a timing path in a static timing analysis of a design of an integrated circuit (IC) with a transient power supply are disclosed. A static timing slack analysis is performed at a selected endpoint in an IC to obtain a candidate timing path leading to the endpoint with a worst static timing slack. A transient static timing slack is determined for the candidate timing path for each clock cycle of a clock signal under the transient power supply. The determined transient static timing slack is used to adjust the timing of the IC and to modify the static timing slack of the candidate timing path.

摘要翻译： 公开了一种用于在具有瞬态电源的集成电路（IC）的设计的静态时序分析中分析和修改定时路径的静态定时松弛的方法，系统和计算机程序产品。 在IC中的选定端点处执行静态时序松弛分析，以获得以最差的静态时序松弛通向端点的候选定时路径。 瞬态电源下的时钟信号的每个时钟周期的候选定时路径确定瞬态静态时序松弛。 使用确定的瞬态静态时序松弛来调整IC的定时并修改候选定时路径的静态时序松弛。