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1.发明授权Low insertion delay clock doubler and integrated circuit clock distribution system using same 有权低插入延迟时钟倍频器和集成电路时钟分配系统使用相同公开(公告)号：US09372499B2
公开(公告)日：2016-06-21
申请号：US14159967
申请日：2014-01-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Sriram Sambamurthy , Arun Sundaresan Iyer , Alok Baluni , Aaron Grenat
CPC classification number: G06F1/04 , G06F1/10 , H03K5/00006 , H03K19/0013 , H03K19/20
Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.
Abstract translation: 时钟倍频器包括具有用于接收时钟输入信号和第二输入的第一输入的第一NAND门，具有第一输入和第二输入的第二NAND门，用于接收时钟输入信号的补码;输出NAND门，具有 分别耦合到第一和非门的输出的第一和第二输入以及用于提供时钟输出信号的输出，具有用于接收时钟输入信号的输入的反相器链，并响应第一和第二控制信号选择性地 向第二NAND门的第一输入提供第一真实输出，以及向第一NAND门的第二输入提供第二互补输出;以及控制信号生成电路，响应于第一NAND门的输出而提供第一和第二控制信号 第一和第二NAND门。
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2.发明申请LOW INSERTION DELAY CLOCK DOUBLER AND INTEGRATED CIRCUIT CLOCK DISTRIBUTION SYSTEM USING SAME 有权低插入延迟时钟双工器和集成电路时钟分配系统公开(公告)号：US20150205323A1
公开(公告)日：2015-07-23
申请号：US14159967
申请日：2014-01-21
Applicant: Advanced Micro Devices, Inc.
Inventor： Sriram Sambamurthy , Arun Sundaresan Iyer , Alok Baluni , Aaron Grenat
CPC classification number: G06F1/04 , G06F1/10 , H03K5/00006 , H03K19/0013 , H03K19/20
Abstract: A clock doubler includes a first NAND gate having a first input for receiving a clock input signal and a second input, a second NAND gate having a first input and a second input for receiving a complement of the clock input signal, an output NAND gate having a first and second inputs coupled to outputs of the first and second NAND gates, respectively, and an output for providing a clock output signal, an inverter chain having an input for receiving the clock input signal and responsive to first and second control signals to selectively provide a first true output to the first input of the second NAND gate, and a second complementary output to the second input of the first NAND gate, and a control signal generation circuit providing the first and second control signals in response to the outputs of the first and second NAND gates.
Abstract translation: 时钟倍频器包括具有用于接收时钟输入信号和第二输入的第一输入的第一NAND门，具有第一输入和第二输入的第二NAND门，用于接收时钟输入信号的补码;输出NAND门，具有 分别耦合到第一和非门的输出的第一和第二输入以及用于提供时钟输出信号的输出，具有用于接收时钟输入信号的输入的反相器链，并响应第一和第二控制信号选择性地 向第二NAND门的第一输入提供第一真实输出，以及向第一NAND门的第二输入提供第二互补输出;以及控制信号生成电路，响应于第一与非门的输出而提供第一和第二控制信号 第一和第二NAND门。
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