公开(公告)号：US10133574B2

公开(公告)日：2018-11-20

申请号：US15181837

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Akanksha Jain ,  Wei Huang ,  Indrani Paul

IPC: G06F9/30 ,  G06F1/32

Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.

公开(公告)号：US20170357509A1

公开(公告)日：2017-12-14

申请号：US15181837

申请日：2016-06-14

Applicant: Advanced Micro Devices, Inc.

Inventor： Akanksha Jain ,  Wei Huang ,  Indrani Paul

IPC: G06F9/30 ,  G06F1/32

CPC classification number: G06F9/30181 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3243 ,  G06F1/3296 ,  G06F11/30

Abstract: A system-on-a-chip includes a plurality of instruction processors and a hardware block such as a system management unit. The hardware block accesses values of performance counters associated with the plurality of instruction processors and modifies one or more operating points of one or more of the plurality of instruction processors based on comparisons of the instruction arrival rates and the instruction service rates to achieve optimized system metrics.