公开(公告)号：US20250110864A1

公开(公告)日：2025-04-03

申请号：US18478016

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Parvez Kashem ,  Alicia Wen Ju Yurie Leong ,  Glennis Eliagh Covington

IPC: G06F12/02 ,  G06F13/16 ,  G11C11/4076

Abstract: Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain the interface.

公开(公告)号：US20250004662A1

公开(公告)日：2025-01-02

申请号：US18342186

申请日：2023-06-27

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： David Da Wei Lin ,  Ronald Lee Pettyjohn ,  Pouya Najafi Ashtiani ,  Gershom Birk ,  Anwar Parvez Kashem

IPC: G06F3/06

Abstract: In accordance with described techniques for read gate training and tracking, a computing device includes a memory system (e.g., dynamic random access memory (DRAM)) that receives a memory read operation which includes a memory clock that correlates to a physical layer (PHY) clock. The computing device includes a PHY that receives a return data signal from the memory system, where the return data signal includes a returned data strobe that is out-of-phase with respect to the PHY clock. The computing device includes training logic that utilizes edge detection to determine an unknown clocking phase of the returned data strobe with respect to the PHY clock. The computing device also includes tracking logic that utilizes the edge detection to detect a signal drift of the delay signal with respect to the returned data strobe and compensate for the drift.

公开(公告)号：US12265467B1

公开(公告)日：2025-04-01

申请号：US18478016

申请日：2023-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Parvez Kashem ,  Alicia Wen Ju Yurie Leong ,  Glennis Eliagh Covington

IPC: G06F12/00 ,  G06F12/02 ,  G06F13/16 ,  G11C11/4076

Abstract: Enhanced methods for memory context restore are described. A device may include a physical layer (PHY) having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface, detect values of a plurality of parameters as part of training the interface, and store the detected values as initial training data. The PHY also implements a retraining mode to use the initial training data as seed data to retrain the interface.

公开(公告)号：US20240371427A1

公开(公告)日：2024-11-07

申请号：US18310872

申请日：2023-05-02

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Tsun-Ho Liu ,  Anwar Parvez Kashem ,  Pouya Najafi Ashtiani ,  Wei Qing Xie

IPC: G11C11/406 ,  G11C11/4074 ,  G11C11/4093

Abstract: A memory system includes a memory controller, a physical layer (PHY), and a memory (e.g., DRAM). Data is written to and read from the memory in different manners for different memory technologies, such as using different signals or signal timings for different memory technologies. Various runtime services specific to the memory technology are performed by the PHY rather than the memory controller. Examples of such runtime services include performing a training routine to train or re-train an interface between the PHY and the memory, performing a power management routine (e.g., to put the main memory in a self-refresh mode), and so forth.

公开(公告)号：US20240355379A1

公开(公告)日：2024-10-24

申请号：US18305080

申请日：2023-04-21

Applicant: Advanced Micro Devices, Inc.

Inventor： Anwar Parvez Kashem ,  Glennis Eliagh Covington ,  Alicia Wen Ju Yurie Leong

IPC: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

CPC classification number: G11C11/4096 ,  G11C11/4074 ,  G11C11/4076

Abstract: Voltage range for training physical memory is described. A device is configurable to include a PHY having an interface to support communication of command signals and data with a physical memory. The PHY implements a training mode to train the interface over a training voltage range to communicate the command signals or data and an operational mode to use the trained interface to communicate the command signals or data over an operational voltage range that is smaller than the training voltage range.

公开(公告)号：US20240329839A1

公开(公告)日：2024-10-03

申请号：US18190724

申请日：2023-03-27

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Tsun-Ho Liu ,  Anwar Parvez Kashem ,  Pouya Najafi Ashtiani ,  Gershom Birk ,  David Da Wei Lin

IPC: G06F3/06 ,  G06F1/08 ,  H04L7/00

CPC classification number: G06F3/0611 ,  G06F1/08 ,  G06F3/0656 ,  G06F3/0673 ,  H04L7/0016

Abstract: Clock domain phase adjustment techniques and systems for memory operations are described. In one example, a physical memory is communicatively coupled to a physical layer via a first clock domain and a memory controller is communicatively coupled to the physical layer via a second clock domain that is different than the first clock domain. A buffer is implemented in the physical layer. The buffer is configured to set a phase adjustment for a latency setting between the first and second clock domains. The phase adjustment is based on whether a mismatch has occurred in data output by the buffer to the memory controller based on a comparison to the latency setting.