公开(公告)号：US20240005078A1

公开(公告)日：2024-01-04

申请号：US17854516

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Edward Griffith ,  Aaron Keiichi Horiuchi ,  Donald A. Clay ,  Eric William Busta ,  Hye Jung Stanford ,  Kathryn E. Wilcox ,  Ruochen Xie ,  Russell Schreiber ,  Stephen J. Dussinger ,  William Edwin Laub, JR. ,  Te-Hsuan Chen

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.