公开(公告)号：US11189569B2

公开(公告)日：2021-11-30

申请号：US15275028

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Richard T. Schultz ,  Regina Tien Schmidt ,  Derek P. Peterson ,  Te-Hsuan Chen ,  Elizabeth C. Conrad ,  Catherina Simona Matheis Ionescu ,  Chu-Wen Wang

IPC: H01L23/528 ,  H01L27/118 ,  G06F30/392 ,  G06F30/394 ,  H01L23/522 ,  H01L27/02 ,  H01L49/02

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.

公开(公告)号：US20240005078A1

公开(公告)日：2024-01-04

申请号：US17854516

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Michael Edward Griffith ,  Aaron Keiichi Horiuchi ,  Donald A. Clay ,  Eric William Busta ,  Hye Jung Stanford ,  Kathryn E. Wilcox ,  Ruochen Xie ,  Russell Schreiber ,  Stephen J. Dussinger ,  William Edwin Laub, JR. ,  Te-Hsuan Chen

IPC: G06F30/392

CPC classification number: G06F30/392 ,  G06F30/398

Abstract: A system and method for efficiently designing a through silicon via (TSV) macro blocks are described. In various implementations, the circuitry of a processor executes instructions of a place and route tool that provides automatic placement of macro blocks and standard cells on an integrated circuit die based on a copy of a netlist of the integrated circuit being designed and a copy of a standard cell library that includes a variety of standard cells and macro blocks. The processor places two functional macros in the floorplan with a channel between them. In the channel, the processor places a TSV macro that includes at least one boundary cell inside of the TSV macro. The processor prevents placement of a boundary cell adjacent to at least one side of the TSV macro despite empty space exists due to no standard cells or macros about the at least one side.

公开(公告)号：US20180090440A1

公开(公告)日：2018-03-29

申请号：US15275028

申请日：2016-09-23

Applicant: Advanced Micro Devices, Inc. ,  ATI Technologies ULC

Inventor： Richard T. Schultz ,  Regina Tien Schmidt ,  Derek P. Peterson ,  Te-Hsuan Chen ,  Elizabeth C. Conrad ,  Catherina Simona Matheis Ionescu ,  Chu-Wen Wang

IPC: H01L23/528 ,  H01L23/522 ,  H01L27/02 ,  G06F17/50

CPC classification number: H01L23/5286 ,  G06F17/5072 ,  G06F17/5077 ,  H01L23/5223 ,  H01L23/5226 ,  H01L27/0207 ,  H01L27/11807 ,  H01L28/60 ,  H01L2027/11811

Abstract: Integrated circuit layouts are disclosed that include metal layers with metal tracks having separate metal sections along the metal tracks. The separate metal sections along a single track may be electrically isolated from each other. The separate metal sections may then be electrically connected to different voltage tracks in metal layers above and/or below the metal layer with the separate metal sections. One or more of the metal layers in the integrated circuit layouts may also include metal tracks at different voltages (e.g., power and ground) that are adjacent to each other within a power grid layout. The metal tracks may be separated by electrically insulating material. The metal tracks and the electrically insulating material between the tracks may create capacitance in the power grid layout.