公开(公告)号：US20220283955A1

公开(公告)日：2022-09-08

申请号：US17752244

申请日：2022-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley ,  William E. Jones

IPC: G06F12/12 ,  G06F12/0862 ,  G06F12/0891

Abstract: A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.

公开(公告)号：US20180052779A1

公开(公告)日：2018-02-22

申请号：US15292777

申请日：2016-10-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley ,  William E. Jones

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0862

Abstract: A data cache region prefetcher creates a region when a data cache miss occurs. Each region includes a predetermined range of data lines proximate to each data cache miss and is tagged with an associated instruction pointer register (RIP). The data cache region prefetcher compares subsequent memory requests against the predetermined range of data lines for each of the existing regions. For each match, the data cache region prefetcher sets an access bit and attempts to identify a pseudo-random access pattern based on the set access bits. The data cache region prefetcher increments or decrements appropriate counters to track how often the pseudo-random access pattern occurs. If the pseudo-random access pattern occurs frequently, then the next time a memory request is processed with the same RIP and pattern, the data cache region prefetcher prefetches the data lines in accordance with the pseudo-random access pattern for that RIP.

公开(公告)号：US12204459B2

公开(公告)日：2025-01-21

申请号：US17752244

申请日：2022-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley ,  William E. Jones

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/0846 ,  G06F12/0886

Abstract: A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.

公开(公告)号：US20140101388A1

公开(公告)日：2014-04-10

申请号：US13648733

申请日：2012-10-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley

IPC: G06F12/08

CPC classification number: G06F12/0862

Abstract: A method and apparatus for controlling the aggressiveness of a prefetcher based on thrash events is presented. An aggressiveness of a prefetcher for a cache is controlled based upon a number of thrashed cache lines that are replaced by a prefetched cache line and subsequently written back into the cache before the prefetched cache line has been accessed.

Abstract translation: 提出了一种基于捶打事件来控制预取器的攻击性的方法和装置。 基于由预取的高速缓存行替换的陡峭的高速缓存行的数量来控制缓存的预取器的侵略性，并且在访问预取的高速缓存行之前随后将其写回高速缓存。