公开(公告)号：US20220292019A1

公开(公告)日：2022-09-15

申请号：US17705864

申请日：2022-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  William E. Jones

IPC: G06F12/0862 ,  G06F11/30 ,  G06F13/16 ,  G06F12/0811

Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.

公开(公告)号：US11675703B2

公开(公告)日：2023-06-13

申请号：US17705864

申请日：2022-03-28

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  William E. Jones

IPC: G06F12/08 ,  G06F12/0862 ,  G06F11/30 ,  G06F13/16 ,  G06F12/0811

CPC classification number: G06F12/0862 ,  G06F11/3037 ,  G06F12/0811 ,  G06F13/161

Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.

公开(公告)号：US20180052779A1

公开(公告)日：2018-02-22

申请号：US15292777

申请日：2016-10-13

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley ,  William E. Jones

IPC: G06F12/12 ,  G06F12/0891 ,  G06F12/0862

Abstract: A data cache region prefetcher creates a region when a data cache miss occurs. Each region includes a predetermined range of data lines proximate to each data cache miss and is tagged with an associated instruction pointer register (RIP). The data cache region prefetcher compares subsequent memory requests against the predetermined range of data lines for each of the existing regions. For each match, the data cache region prefetcher sets an access bit and attempts to identify a pseudo-random access pattern based on the set access bits. The data cache region prefetcher increments or decrements appropriate counters to track how often the pseudo-random access pattern occurs. If the pseudo-random access pattern occurs frequently, then the next time a memory request is processed with the same RIP and pattern, the data cache region prefetcher prefetches the data lines in accordance with the pseudo-random access pattern for that RIP.

公开(公告)号：US11620224B2

公开(公告)日：2023-04-04

申请号：US16709831

申请日：2019-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Aparna Thyagarajan ,  Ashok Tirupathy Venkatachar ,  Marius Evers ,  Angelo Wong ,  William E. Jones

IPC: G06F12/0862 ,  G06F12/0875

Abstract: Techniques for controlling prefetching of instructions into an instruction cache are provided. The techniques include tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the tracking, and adjusting prefetch activity based on the throttle toggle.

公开(公告)号：US20220283955A1

公开(公告)日：2022-09-08

申请号：US17752244

申请日：2022-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley ,  William E. Jones

IPC: G06F12/12 ,  G06F12/0862 ,  G06F12/0891

Abstract: A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.

公开(公告)号：US12204459B2

公开(公告)日：2025-01-21

申请号：US17752244

申请日：2022-05-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Donald W. McCauley ,  William E. Jones

IPC: G06F12/08 ,  G06F12/0862 ,  G06F12/0891 ,  G06F12/12 ,  G06F12/0846 ,  G06F12/0886

Abstract: A method, system, and processing system for pre-fetching data is disclosed. The method, system, and processing system includes data cache region prefetch circuitry for detecting a first access by a first instruction at a first instruction address to a first memory portion, detecting a first non-sequential access pattern to a set of addresses in the first memory portion, and in response to a miss by a second instruction at the first instruction address, and in response to the non-sequential access pattern occurring, pre-fetching data according to the first non-sequential access pattern.

公开(公告)号：US11561906B2

公开(公告)日：2023-01-24

申请号：US15839089

申请日：2017-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  William E. Jones

IPC: G06F12/12 ,  G06F12/128 ,  G06F12/0882

Abstract: A processing system rinses, from a cache, those cache lines that share the same memory page as a cache line identified for eviction. A cache controller of the processing system identifies a cache line as scheduled for eviction. In response, the cache controller, identifies additional “dirty victim” cache lines (cache lines that have been modified at the cache and not yet written back to memory) that are associated with the same memory page, and writes each of the identified cache lines to the same memory page. By writing each of the dirty victim cache lines associated with the memory page to memory, the processing system reduces memory overhead and improves processing efficiency.

公开(公告)号：US11294810B2

公开(公告)日：2022-04-05

申请号：US15838809

申请日：2017-12-12

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： William L. Walker ,  William E. Jones

IPC: G06F12/08 ,  G06F12/0862 ,  G06F11/30 ,  G06F13/16 ,  G06F12/0811

Abstract: A processing system includes an interconnect fabric coupleable to a local memory and at least one compute cluster coupled to the interconnect fabric. The compute cluster includes a processor core and a cache hierarchy. The cache hierarchy has a plurality of caches and a throttle controller configured to throttle a rate of memory requests issuable by the processor core based on at least one of an access latency metric and a prefetch accuracy metric. The access latency metric represents an average access latency for memory requests for the processor core and the prefetch accuracy metric represents an accuracy of a prefetcher of a cache of the cache hierarchy.

公开(公告)号：US20210173783A1

公开(公告)日：2021-06-10

申请号：US16709831

申请日：2019-12-10

Applicant: Advanced Micro Devices, Inc.

Inventor： Aparna Thyagarajan ,  Ashok Tirupathy Venkatachar ,  Marius Evers ,  Angelo Wong ,  William E. Jones

IPC: G06F12/0862

Abstract: Techniques for controlling prefetching of instructions into an instruction cache are provided. The techniques include tracking either or both of branch target buffer misses and instruction cache misses, modifying a throttle toggle based on the tracking, and adjusting prefetch activity based on the throttle toggle.