公开(公告)号：US20220197809A1

公开(公告)日：2022-06-23

申请号：US17133581

申请日：2020-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Furkan Eris ,  Paul S. Keltcher ,  John Kalamatianos ,  Mayank Chhablani ,  Alok Garg

IPC: G06F12/0862 ,  G06N20/00 ,  G06F16/901

Abstract: Techniques for identifying a hardware configuration for operation are disclosed. The techniques include applying feature measurements to a trained model; obtaining output values from the trained model, the output values corresponding to different hardware configurations; and operating according to the output values, wherein the output values include one of a certainty score, a ranking, or a regression value.

公开(公告)号：US12045169B2

公开(公告)日：2024-07-23

申请号：US17133581

申请日：2020-12-23

Applicant: Advanced Micro Devices, Inc.

Inventor： Furkan Eris ,  Paul S. Keltcher ,  John Kalamatianos ,  Mayank Chhablani ,  Alok Garg

IPC: G06F12/0862 ,  G06F16/901 ,  G06N20/00

CPC classification number: G06F12/0862 ,  G06F16/9027 ,  G06N20/00

Abstract: Techniques for identifying a hardware configuration for operation are disclosed. The techniques include applying feature measurements to a trained model; obtaining output values from the trained model, the output values corresponding to different hardware configurations; and operating according to the output values, wherein the output values include one of a certainty score, a ranking, or a regression value.

公开(公告)号：US20250077409A1

公开(公告)日：2025-03-06

申请号：US18240640

申请日：2023-08-31

Applicant: Advanced Micro Devices, Inc ,  ATI Technologies ULC

Inventor： Kishore Punniyamurthy ,  Richard David Sodke ,  Furkan Eris ,  Sergey Blagodurov ,  Bradford Michael Beckmann ,  Brandon Keith Potter ,  Khaled Hamidouche

IPC: G06F12/02 ,  G06F13/16

Abstract: A device includes a plurality of processing elements (PEs). A symmetric memory is allocated in each of the plurality of PEs. The device includes a switch connected to the plurality of PEs. The switch is to: receive, from a first processing element (PE) of the plurality of PEs, a message that includes a buffer offset, compute, based on the buffer offset, a first memory address of a first buffer in a first symmetric memory of the first PE and a second memory address of a second buffer in a second symmetric memory of a second PE of the plurality of PEs, and initiate, based on the first memory address and the second memory address, a direct memory access operation to access the first buffer and the second buffer.

公开(公告)号：US11455252B2

公开(公告)日：2022-09-27

申请号：US16454027

申请日：2019-06-26

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Paul S. Keltcher ,  Mayank Chhablani ,  Alok Garg ,  Furkan Eris

IPC: G06F12/0862 ,  G06F16/22 ,  G06N20/20

Abstract: Techniques for generating a model for predicting when different hybrid prefetcher configurations should be used are disclosed. Techniques for using the model to predict when different hybrid prefetcher configurations should be used are also disclosed. The techniques for generating the model include obtaining a set of input data, and generating trees based on the training data. Each tree is associated with a different hybrid prefetcher configuration and the trees output certainty scores for the associated hybrid prefetcher configuration based on hardware feature measurements. To decide on a hybrid prefetcher configuration to use, a prefetcher traverses multiple trees to obtain certainty scores for different hybrid prefetcher configurations and identifies a hybrid prefetcher configuration to used based on a comparison of the certainty scores.