公开(公告)号：US09213355B2

公开(公告)日：2015-12-15

申请号：US13670086

申请日：2012-11-06

Applicant: Advanced Micro Devices, Inc.

Inventor： Gordon F. Caruk ,  Gerald R. Talbot

IPC: G06F1/00 ,  G06F5/06 ,  H04L7/00 ,  H04L7/04

CPC classification number: G06F1/00 ,  G06F1/04 ,  G06F5/06 ,  H04L7/00 ,  H04L7/005 ,  H04L2007/045

Abstract: In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device having capability to compensate for a clock frequency mismatch. A device includes an interconnect interface comprising a transmit port and a receive port, and a configuration structure. The configuration structure comprises a capability field to store a value indicating whether the device has a capability to compensate for a clock frequency mismatch, and an enable field. The device further includes a packet control module to configure a rate of insertion of clock mismatch compensation symbols by the transmit port into a data stream responsive to a value stored at the enable field.

Abstract translation: 在包括通过互连耦合的第一设备和第二设备的系统中，一种方法包括将响应于第二设备的多个插入速率的第一设备的发送端口的时钟失配补偿符号的插入速率设置为 器件具有补偿时钟频率不匹配的能力。 一种设备包括包括发送端口和接收端口的互连接口以及配置结构。 配置结构包括存储指示设备是否具有补偿时钟频率失配的能力的值的能力字段和启用字段。 该设备还包括分组控制模块，用于响应于存储在启用字段的值，将发送端口的时钟失配补偿符号的速率配置成数据流。

公开(公告)号：US20140129867A1

公开(公告)日：2014-05-08

申请号：US13670086

申请日：2012-11-06

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Gordon F. Caruk ,  Gerald R. Talbot

IPC: G06F1/00

CPC classification number: G06F1/00 ,  G06F1/04 ,  G06F5/06 ,  H04L7/00 ,  H04L7/005 ,  H04L2007/045

Abstract: In a system comprising a first device and a second device coupled via an interconnect, a method includes setting a rate of insertion of clock mismatch compensation symbols for a transmit port of the first device to one of a plurality of rates of insertion responsive to the second device having capability to compensate for a clock frequency mismatch. A device includes an interconnect interface comprising a transmit port and a receive port, and a configuration structure. The configuration structure comprises a capability field to store a value indicating whether the device has a capability to compensate for a clock frequency mismatch, and an enable field. The device further includes a packet control module to configure a rate of insertion of clock mismatch compensation symbols by the transmit port into a data stream responsive to a value stored at the enable field.

Abstract translation: 在包括通过互连耦合的第一设备和第二设备的系统中，一种方法包括将响应于第二设备的多个插入速率的第一设备的发送端口的时钟失配补偿符号的插入速率设置为 器件具有补偿时钟频率不匹配的能力。 一种设备包括包括发送端口和接收端口的互连接口以及配置结构。 配置结构包括存储指示设备是否具有补偿时钟频率失配的能力的值的能力字段和启用字段。 该设备还包括分组控制模块，用于响应于存储在启用字段的值，将发送端口的时钟失配补偿符号的速率配置成数据流。