公开(公告)号：US20130290767A1

公开(公告)日：2013-10-31

申请号：US13920251

申请日：2013-06-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron J. NYGREN ,  Ming-Ju E. Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan D. Pham ,  W. Fritz Kruger ,  Michael J. Litt

IPC: G06F1/14

CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.

Abstract translation: 提供了用于调整写入时序的装置。 例如，该装置可以包括地址/控制总线，写时钟数据恢复（WCDR）信号总线和定时调整模块。 地址/控制总线可以被配置为同时启用WCDR操作模式和主动操作模式。 WCDR信号总线可以被配置为在WCDR操作模式期间将WCDR数据发送到存储器件。 并且定时调整模块可以被配置为基于WCDR数据中的相移来调整定时。

公开(公告)号：US09798353B2

公开(公告)日：2017-10-24

申请号：US13920251

申请日：2013-06-18

Applicant: Advanced Micro Devices, Inc.

Inventor： Aaron J. Nygren ,  Ming-Ju E. Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan D. Pham ,  W. Fritz Kruger ,  Michael J. Litt

IPC: G06F1/12 ,  G06F1/14 ,  G06F1/08 ,  G06F13/16

CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.