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    Adjustment of write timing in a memory device
    1.
    发明授权
    Adjustment of write timing in a memory device 有权
    调整存储设备中的写入时序

    公开(公告)号：US09508408B2

    公开(公告)日：2016-11-29

    申请号：US14243283

    申请日：2014-04-02

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Ming-Ju Edward Lee ,  Shadi M. Barakat ,  Warren Fritz Kruger ,  Xiaoling Xu ,  Toan Duc Pham ,  Aaron John Nygren

    IPC: G11C7/00 ,  G11C7/22 ,  G06F13/16 ,  G06F13/42 ,  G11C11/4076

    CPC classification number: G11C7/22 ,  G06F13/1689 ,  G06F13/4234 ,  G11C7/222 ,  G11C11/4076

    Abstract: A method and system are provided for adjusting a write timing in a memory device. For instance, the method can include receiving a data signal, a write clock signal, and a reference signal. The method can also include detecting a phase shift in the reference signal over time. The phase shift of the reference signal can be used to adjust a phase difference between the data signal and the write clock signal, where the memory device recovers data from the data signal based on an adjusted write timing of the data signal and the write clock signal.

    Abstract translation: 提供了一种用于调整存储器件中的写时序的方法和系统。 例如，该方法可以包括接收数据信号，写时钟信号和参考信号。 该方法还可以包括随时间检测参考信号中的相移。 参考信号的相移可用于调整数据信号和写入时钟信号之间的相位差，其中存储器件基于数据信号和写入时钟信号的调整的写入定时从数据信号中恢复数据 。

    COMMAND PROTOCOL FOR ADJUSTMENT OF WRITE TIMING DELAY
    3.
    发明申请
    COMMAND PROTOCOL FOR ADJUSTMENT OF WRITE TIMING DELAY 有权
    用于调整写入时间延迟的命令协议

    公开(公告)号：US20130290767A1

    公开(公告)日：2013-10-31

    申请号：US13920251

    申请日：2013-06-18

    Applicant: Advanced Micro Devices, Inc.

    Inventor： Aaron J. NYGREN ,  Ming-Ju E. Lee ,  Shadi M. Barakat ,  Xiaoling Xu ,  Toan D. Pham ,  W. Fritz Kruger ,  Michael J. Litt

    IPC: G06F1/14

    CPC classification number: G06F1/14 ,  G06F1/08 ,  G06F13/1689

    Abstract: Apparatuses are provided for adjusting the write timing. For instance, the apparatus can include an address/control bus, a write clock data recovery (WCDR) signal bus, and a timing adjustment module. The address/control bus can be configured to concurrently enable a WCDR mode of operation and an active mode of operation. The WCDR signal bus can be configured to transmit WCDR data to a memory device during the WCDR mode of operation. And the timing adjustment module can be configured to adjust a timing based on a phase shift in the WCDR data.

    Abstract translation: 提供了用于调整写入时序的装置。 例如，该装置可以包括地址/控制总线，写时钟数据恢复（WCDR）信号总线和定时调整模块。 地址/控制总线可以被配置为同时启用WCDR操作模式和主动操作模式。 WCDR信号总线可以被配置为在WCDR操作模式期间将WCDR数据发送到存储器件。 并且定时调整模块可以被配置为基于WCDR数据中的相移来调整定时。

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