公开(公告)号：US20180114555A1

公开(公告)日：2018-04-26

申请号：US15299709

申请日：2016-10-21

申请人： Advanced Micro Devices, Inc.

发明人： John J. Wuu ,  Ryan Freese ,  Russell J. Schreiber

IPC分类号： G11C7/12 ,  H03K19/0185 ,  G11C7/06 ,  G11C7/22

CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/222 ,  G11C7/225 ,  H03K19/00323 ,  H03K19/018507

摘要： An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.

公开(公告)号：US09953687B1

公开(公告)日：2018-04-24

申请号：US15299709

申请日：2016-10-21

申请人： Advanced Micro Devices, Inc.

发明人： John J. Wuu ,  Ryan Freese ,  Russell J. Schreiber

IPC分类号： G11C11/41 ,  G11C11/419 ,  G11C7/12 ,  H03K19/0185 ,  G11C7/06 ,  G11C7/22

CPC分类号： G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/222 ,  G11C7/225 ,  H03K19/00323 ,  H03K19/018507

摘要： An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.