公开(公告)号：US20230100607A1

公开(公告)日：2023-03-30

申请号：US17488519

申请日：2021-09-29

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu ,  Keith A. Kasprak

IPC: G11C11/419

Abstract: A technique reduces power consumption of a bit cell in a memory and provides write assistance to the bit cell. When the bit cell is active, a power-saving write-assist circuit coupled to the bit cell is selectively sized according to a type of memory access. When the bit cell is inactive, the virtual power supply node floats to a predetermined voltage between a first voltage on a first power supply node coupled to the bit cell and a second voltage on a second power supply node coupled to the bit cell. A method for controlling power consumption of a bit cell and assisting a write to the bit cell includes providing a reference voltage to a virtual power supply node coupled to the bit cell. The reference voltage is provided based on an operational state of the bit cell and a type of memory access to the bit cell.

公开(公告)号：US11610627B2

公开(公告)日：2023-03-21

申请号：US17359254

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell J. Schreiber ,  John J. Wuu

IPC: G11C7/10 ,  G11C11/4096 ,  G11C11/408 ,  G11C11/4074

Abstract: A write masked latch bit cell of an SRAM includes a write mask circuit that is responsive to assertion of a first write mask signal to cause a value of a write data node to be a first value and is responsive to assertion of a second write mask signal to cause the value of the write data node to have a second value. A pass gate supplies the data on the write data node to an internal node of the bit cell responsive to write word line signals being asserted. A keeper circuit maintains the value of the first node independently of values of the write word line signals while the first write mask signal and the second write mask signal are deasserted.

公开(公告)号：US20220415377A1

公开(公告)日：2022-12-29

申请号：US17359445

申请日：2021-06-25

Applicant: Advanced Micro Devices, Inc.

Inventor： Arijit Banerjee ,  John J. Wuu ,  Russell Schreiber

IPC: G11C8/16 ,  G11C11/418 ,  G11C11/419 ,  G06F30/392

Abstract: An apparatus and method for providing efficient floor planning, power, and performance tradeoffs of memory accesses. A dual read port and single write port memory bit cell uses two asymmetrical read access circuits for conveying stored data on two read bit lines. The two read bit lines are pre-charged to different voltage reference levels. The layout of the memory bit cell places the two read bit lines on an opposed edge from the single write bit line. The layout uses a dummy gate placed over both p-type diffusion and n-type diffusion between the edges. The layout has a same number of p-type transistors as n-type transistors despite using asymmetrical read access circuits. The layout also has a contacted gate pitch that is one more than the number of p-type transistors.

公开(公告)号：US20190334524A1

公开(公告)日：2019-10-31

申请号：US15965186

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Edward Chang

IPC: H03K19/00 ,  G11C11/412 ,  G11C11/419 ,  G06F3/06

Abstract: Systems, apparatuses, and methods for efficiently performing operations system are disclosed. A computing system uses a memory for storing data, and one or more processing units. The memory includes multiple rows for storing the data with each intersection of a row and a column being a memory bit cell. The memory processes operations. For particular operations, the two or more operands are accessed simultaneously for generating a result without being read out and stored. Two indications are generated specifying at least a first row and a second row targeted by the operation. The memory generates a result by performing the operation for each of the one or more cells in the first row a stored value with a respective stored value in the one or more cells in the second row.

公开(公告)号：US20180114555A1

公开(公告)日：2018-04-26

申请号：US15299709

申请日：2016-10-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Ryan Freese ,  Russell J. Schreiber

IPC: G11C7/12 ,  H03K19/0185 ,  G11C7/06 ,  G11C7/22

CPC classification number: G11C7/12 ,  G11C5/14 ,  G11C7/08 ,  G11C7/222 ,  G11C7/225 ,  H03K19/00323 ,  H03K19/018507

Abstract: An interlock circuit utilizes a single combinatorial pseudo-dynamic logic gate to take inputs from two voltage domains at the same time without requiring either input to be level shifted. The interlock design allows hold timing to be met across a large voltage range of both supplies in a dual-voltage supply environment while not significantly hurting setup time by having much lower latency than the latency of a level shifter.

公开(公告)号：US09159409B2

公开(公告)日：2015-10-13

申请号：US13623937

申请日：2012-09-21

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Donald R. Weiss

IPC: G11C14/00 ,  G11C13/00

CPC classification number: G11C13/0004 ,  G11C13/0007 ,  G11C13/0033 ,  G11C13/0061 ,  G11C14/0081 ,  G11C14/009 ,  G11C2213/77

Abstract: A method, integrated circuit and apparatus are operative to control a plurality of passive variable resistance memory cells to store complimentary state information from at least one active memory circuit, such as a flop, latch, or any other suitable state generation circuit. The method, apparatus and integrated circuit may be operative to control the plurality of passive variable resistance memory cells to also restore the stored complimentary state information for the at least one active memory.

Abstract translation: 一种方法，集成电路和装置可操作以控制多个可变电阻存储器单元以从至少一个有效存储器电路（诸如触发器，锁存器或任何其它合适的状态产生电路）存储互补状态信息。 该方法，装置和集成电路可操作以控制多个可变电阻存储器单元，以还恢复存储的至少一个有效存储器的互补状态信息。

公开(公告)号：US20240063206A1

公开(公告)日：2024-02-22

申请号：US18497961

申请日：2023-10-30

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Milind Bhagavat ,  Brett Wilkerson ,  Rahul Agarwal

IPC: H01L25/18 ,  H01L23/48 ,  H01L23/528 ,  H01L23/00

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/528 ,  H01L24/05 ,  H01L24/08 ,  H01L2224/0557 ,  H01L2224/08146

Abstract: Systems, apparatuses, and methods for routing traffic through vertically stacked semiconductor dies are disclosed. A first semiconductor die has a second die stacked vertically on top of it in a three-dimensional integrated circuit. The first die includes a through silicon via (TSV) interconnect that does not traverse the first die. The first die includes one or more metal layers above the TSV, which connect to a bonding pad interface through a bonding pad via. If the signals transferred through the TSV of the first die are shared by the second die, then the second die includes a TSV aligned with the bonding pad interface of the first die. If these signals are not shared by the second die, then the second die includes an insulated portion of a wafer backside aligned with the bonding pad interface.

公开(公告)号：US11233510B2

公开(公告)日：2022-01-25

申请号：US15965186

申请日：2018-04-27

Applicant: Advanced Micro Devices, Inc.

Inventor： John J. Wuu ,  Edward Chang

IPC: G11C7/06 ,  H03K19/00 ,  G11C11/412 ,  G11C11/419 ,  G06F3/06 ,  G11C11/418

Abstract: Systems, apparatuses, and methods for efficiently performing operations system are disclosed. A computing system uses a memory for storing data, and one or more processing units. The memory includes multiple rows for storing the data with each intersection of a row and a column being a memory bit cell. The memory processes operations. For particular operations, the two or more operands are accessed simultaneously for generating a result without being read out and stored. Two indications are generated specifying at least a first row and a second row targeted by the operation. The memory generates a result by performing the operation for each of the one or more cells in the first row a stored value with a respective stored value in the one or more cells in the second row.

公开(公告)号：US10043572B1

公开(公告)日：2018-08-07

申请号：US15663096

申请日：2017-07-28

Applicant: Advanced Micro Devices, Inc.

Inventor： Russell Schreiber ,  John J. Wuu ,  Keith Kasprak

IPC: G11C11/40 ,  G11C11/419 ,  G11C11/418 ,  G11C5/14 ,  G11C5/06

Abstract: A system and method for providing efficient power, performance and stability tradeoffs of memory accesses are described. A computing system uses a memory for storing data, and a processing unit, which generates access request. The memory stores data and includes a dummy cell between a first region and a second region. The first region and the second region operate with at least one of two operating states such as an awake state and a sleep state. The dummy cell uses two ground connections to support two separate ground references. In one example, a first ground reference is zero volts and a second ground reference is a floating node. In another example, the first ground reference is a value shared by one of the two regions and the second ground reference is the floating node.

公开(公告)号：US20140204658A1

公开(公告)日：2014-07-24

申请号：US13749672

申请日：2013-01-24

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： John J. Wuu ,  Keith A. Kasprak ,  Russell Schreiber

IPC: G11C11/412 ,  G11C7/00

CPC classification number: G11C11/412 ,  G11C7/04

Abstract: An apparatus may comprise a memory cell configured to operate according to a voltage mode, a voltage controller coupled with the memory cell, wherein the voltage controller is configured to change the voltage mode of the memory cell between a low voltage mode and a high voltage mode, and a memory controller module coupled with the memory cell, wherein the memory controller is configured to invert a logic state stored in the memory cell based on the voltage mode.

Abstract translation: 装置可以包括被配置为根据电压模式操作的存储单元，与存储单元耦合的电压控制器，其中电压控制器被配置为在低电压模式和高电压模式之间改变存储单元的电压模式 以及与所述存储器单元耦合的存储器控​​制器模块，其中所述存储器控制器被配置为基于所述电压模式反转存储在所述存储器单元中的逻辑状态。