公开(公告)号：US10949201B2

公开(公告)日：2021-03-16

申请号：US16286702

申请日：2019-02-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Scott Thomas Bingham ,  Marius Evers ,  Krishnan V. Ramani ,  Thomas Kunjan

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815

Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

公开(公告)号：US20240004657A1

公开(公告)日：2024-01-04

申请号：US17855621

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar Arunachalam ,  Manivannan Bhoopathy ,  Hon-Hin Wong ,  Scott Thomas Bingham

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3838

Abstract: The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20200319889A1

公开(公告)日：2020-10-08

申请号：US16671097

申请日：2019-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Susumu Mashimo ,  Krishnan V. Ramani ,  Scott Thomas Bingham

IPC: G06F9/38 ,  G06F9/30

Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.

公开(公告)号：US12118357B2

公开(公告)日：2024-10-15

申请号：US17855621

申请日：2022-06-30

Applicant: Advanced Micro Devices, Inc.

Inventor： Rajesh Kumar Arunachalam ,  Manivannan Bhoopathy ,  Hon-Hin Wong ,  Scott Thomas Bingham

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30145 ,  G06F9/3838

Abstract: The disclosed system may include a processor configured to encode, using an encoding scheme that reduces a number of bits needed to represent one or more instructions from a set of instructions in an instruction buffer represented by a dependency matrix, a dependency indicating that a child instruction represented in the dependency matrix depends on a parent instruction represented in the dependency matrix. The processor may also be configured to store the encoded dependency in the dependency matrix and dispatch instructions in the instruction buffer based at least on decoding one or more dependencies stored in the dependency matrix for the instructions. Various other methods, systems, and computer-readable media are also disclosed.

公开(公告)号：US20200272463A1

公开(公告)日：2020-08-27

申请号：US16286702

申请日：2019-02-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Scott Thomas Bingham ,  Marius Evers ,  Krishnan V. Ramani ,  Thomas Kunjan

IPC: G06F9/30 ,  G06F12/0875

Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

公开(公告)号：US11847463B2

公开(公告)日：2023-12-19

申请号：US16585973

申请日：2019-09-27

Applicant: ADVANCED MICRO DEVICES, INC.

Inventor： Kai Troester ,  Scott Thomas Bingham ,  John M. King ,  Michael Estlick ,  Erik Swanson ,  Robert Weidner

IPC: G06F9/38 ,  G06F9/30

CPC classification number: G06F9/3861 ,  G06F9/30036 ,  G06F9/30038 ,  G06F9/30043 ,  G06F9/3887 ,  G06F9/30018

Abstract: A processor includes a load/store unit and an execution pipeline to execute an instruction that represents a single-instruction-multiple-data (SIMD) operation, and which references a memory block storing operand data for one or more lanes of a plurality of lanes and a mask vector indicating which lanes of a plurality of lanes are enabled and which are disabled for the operation. The execution pipeline executes an instruction in a first execution mode unless a memory fault is generated during execution of the instruction in the first execution mode. In response to the memory fault, the execution pipeline re-executes the instruction in a second execution mode. In the first execution mode, a single load operation is attempted to access the memory block via the load/store unit. In the second execution mode, a separate load operation is performed by the load/store unit for each enabled lane of the plurality of lanes prior to executing the SIMD operation.

公开(公告)号：US11113065B2

公开(公告)日：2021-09-07

申请号：US16671097

申请日：2019-10-31

Applicant: Advanced Micro Devices, Inc.

Inventor： John Kalamatianos ,  Susumu Mashimo ,  Krishnan V. Ramani ,  Scott Thomas Bingham

IPC: G06F9/38 ,  G06F9/30

Abstract: A technique for speculatively executing load-dependent instructions includes detecting that a memory ordering consistency queue is full for a completed load instruction. The technique also includes storing data loaded by the completed load instruction into a storage location for storing data when the memory ordering consistency queue is full. The technique further includes speculatively executing instructions that are dependent on the completed load instruction. The technique also includes in response to a slot becoming available in the memory ordering consistency queue, replaying the load instruction. The technique further includes in response to receiving loaded data for the replayed load instruction, testing for a data mis-speculation by comparing the loaded data for the replayed load instruction with the data loaded by the completed load instruction that is stored in the storage location.