公开(公告)号：US20200272463A1

公开(公告)日：2020-08-27

申请号：US16286702

申请日：2019-02-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Scott Thomas Bingham ,  Marius Evers ,  Krishnan V. Ramani ,  Thomas Kunjan

IPC: G06F9/30 ,  G06F12/0875

Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.

公开(公告)号：US20150121046A1

公开(公告)日：2015-04-30

申请号：US14523730

申请日：2014-10-24

Applicant: Advanced Micro Devices, Inc.

Inventor： Thomas Kunjan ,  Scott T. Bingham ,  Marius Evers ,  James D. Williams

IPC: G06F9/30 ,  G06F12/08

CPC classification number: G06F9/30043 ,  G06F9/3834 ,  G06F9/3855 ,  G06F9/3857 ,  G06F12/0875 ,  G06F12/1027 ,  G06F2212/452 ,  G06F2212/684

Abstract: The present invention provides a method and apparatus for supporting embodiments of an out-of-order load to load queue structure. One embodiment of the apparatus includes a load queue for storing memory operations adapted to be executed out-of-order with respect to other memory operations. The apparatus also includes a load order queue for cacheable operations that ordered for a particular address.

Abstract translation: 本发明提供了一种用于支持负载队列结构的无序负载的实施例的方法和装置。 该装置的一个实施例包括用于存储适于相对于其他存储器操作无序执行的存储器操作的加载队列。 该装置还包括针对特定地址排序的可缓存操作的加载顺序队列。

公开(公告)号：US10949201B2

公开(公告)日：2021-03-16

申请号：US16286702

申请日：2019-02-27

Applicant: Advanced Micro Devices, Inc.

Inventor： Scott Thomas Bingham ,  Marius Evers ,  Krishnan V. Ramani ,  Thomas Kunjan

IPC: G06F9/30 ,  G06F12/0875 ,  G06F12/0815

Abstract: A processor and method for handling lock instructions identifies which of a plurality of older store instructions relative to a current lock instruction are able to be locked. The method and processor lock the identified older store instructions as an atomic group with the current lock instruction. The method and processor negatively acknowledge probes until all of the older store instructions in the atomic group have written to cache memory. In some implementations, an atomic grouping unit issues an indication to lock identified older store instructions that are retired and lockable, and in some implementations, also issues an indication to lock older stores that are determined to be lockable that are non-retired.